X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fppc4xx%2Fcpu.c;h=d9b5d32c90cce95d00a5f23c8519366a39e3c321;hb=0f2859689a283ecb0e3d29e23ff7e21dbb6abb70;hp=a4630530a73d78b3ba56f736617c5fa43e261a90;hpb=a46726fdba86d02353529a98f26cd1384f991d40;p=u-boot

diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index a4630530a7..d9b5d32c90 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2003
+ * (C) Copyright 2000-2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -37,6 +37,10 @@
 #include <asm/cache.h>
 #include <ppc4xx.h>
 
+#if !defined(CONFIG_405)
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 
 #if defined(CONFIG_440)
 #define FREQ_EBC		(sys_info.freqEPB)
@@ -57,7 +61,7 @@ int pci_async_enabled(void)
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 	unsigned long val;
 
-	mfsdr(cpc0_strp1, val);
+	mfsdr(sdr_sdstp1, val);
 	return (val & SDR0_SDSTP1_PAME_MASK);
 #endif
 }
@@ -116,7 +120,6 @@ static int do_chip_reset(unsigned long sys0, unsigned long sys1);
 int checkcpu (void)
 {
 #if !defined(CONFIG_405)	/* not used on Xilinx 405 FPGA implementations */
-	DECLARE_GLOBAL_DATA_PTR;
 	uint pvr = get_pvr();
 	ulong clock = gd->cpu_clk;
 	char buf[32];
@@ -220,12 +223,20 @@ int checkcpu (void)
 	case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
 		puts("EP Rev. B");
 		break;
+
+	case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
+		puts("EP Rev. C");
+		break;
 #endif /*  CONFIG_440EP */
 
 #ifdef CONFIG_440GR
 	case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
 		puts("GR Rev. A");
 		break;
+
+	case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
+		puts("GR Rev. B");
+		break;
 #endif /* CONFIG_440GR */
 #endif /* CONFIG_440 */