X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fppc4xx%2Fcpu.c;h=fb3837c3df7befa480a7fc2ad30b180e41c49019;hb=6973fb414c36b25b4622917d6a223510be0678f5;hp=c07bc0c325e0a9ef5c1f123f6906378c94d14b83;hpb=98c440bee623ecdd5322852732b883e696fb2140;p=u-boot

diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index c07bc0c325..fb3837c3df 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2006
+ * (C) Copyright 2000-2007
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -36,38 +36,40 @@
 #include <command.h>
 #include <asm/cache.h>
 #include <ppc4xx.h>
+#include <netdev.h>
 
-#if !defined(CONFIG_405)
 DECLARE_GLOBAL_DATA_PTR;
-#endif
 
-#if defined(CONFIG_BOARD_RESET)
 void board_reset(void);
-#endif
 
-#if defined(CONFIG_440)
-#define FREQ_EBC		(sys_info.freqEPB)
-#elif defined(CONFIG_405EZ)
-#define FREQ_EBC		((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \
-				 sys_info.pllExtBusDiv)
-#else
-#define FREQ_EBC		(sys_info.freqPLB / sys_info.pllExtBusDiv)
-#endif
+/*
+ * To provide an interface to detect CPU number for boards that support
+ * more then one CPU, we implement the "weak" default functions here.
+ *
+ * Returns CPU number
+ */
+int __get_cpu_num(void)
+{
+	return NA_OR_UNKNOWN_CPU;
+}
+int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
 
+#if defined(CONFIG_PCI)
 #if defined(CONFIG_405GP) || \
     defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 #define PCI_ASYNC
 
-int pci_async_enabled(void)
+static int pci_async_enabled(void)
 {
 #if defined(CONFIG_405GP)
 	return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
 #endif
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	unsigned long val;
 
 	mfsdr(sdr_sdstp1, val);
@@ -75,9 +77,11 @@ int pci_async_enabled(void)
 #endif
 }
 #endif
+#endif /* CONFIG_PCI */
 
-#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
-int pci_arbiter_enabled(void)
+#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
+    !defined(CONFIG_405) && !defined(CONFIG_405EX)
+static int pci_arbiter_enabled(void)
 {
 #if defined(CONFIG_405GP)
 	return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
@@ -98,7 +102,8 @@ int pci_arbiter_enabled(void)
 	return (val & 0x80000000);
 #endif
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	unsigned long val;
 
 	mfsdr(sdr_pci0, val);
@@ -107,14 +112,10 @@ int pci_arbiter_enabled(void)
 }
 #endif
 
-#if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-
+#if defined(CONFIG_405EP)
 #define I2C_BOOTROM
 
-int i2c_bootrom_enabled(void)
+static int i2c_bootrom_enabled(void)
 {
 #if defined(CONFIG_405EP)
 	return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
@@ -183,6 +184,34 @@ static char *bootstrap_str[] = {
 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 #endif
 
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define SDR0_PINSTP_SHIFT	29
+static char *bootstrap_str[] = {
+	"EBC (8 bits)",
+	"EBC (16 bits)",
+	"PCI",
+	"PCI",
+	"EBC (16 bits)",
+	"NAND (8 bits)",
+	"I2C (Addr 0x54)",	/* A8 */
+	"I2C (Addr 0x52)",	/* A4 */
+};
+static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
+#endif
+
+#if defined(CONFIG_460SX)
+#define SDR0_PINSTP_SHIFT	29
+static char *bootstrap_str[] = {
+	"EBC (8 bits)",
+	"EBC (16 bits)",
+	"EBC (32 bits)",
+	"NAND (8 bits)",
+	"I2C (Addr 0x54)",      /* A8 */
+	"I2C (Addr 0x52)",      /* A4 */
+};
+static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
+#endif
+
 #if defined(CONFIG_405EZ)
 #define SDR0_PINSTP_SHIFT	28
 static char *bootstrap_str[] = {
@@ -207,6 +236,21 @@ static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
 				 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
 #endif
 
+#if defined(CONFIG_405EX)
+#define SDR0_PINSTP_SHIFT	29
+static char *bootstrap_str[] = {
+	"EBC (8 bits)",
+	"EBC (16 bits)",
+	"EBC (16 bits)",
+	"NAND (8 bits)",
+	"NAND (8 bits)",
+	"I2C (Addr 0x54)",
+	"EBC (8 bits)",
+	"I2C (Addr 0x52)",
+};
+static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
+#endif
+
 #if defined(SDR0_PINSTP_SHIFT)
 static int bootstrap_option(void)
 {
@@ -219,7 +263,19 @@ static int bootstrap_option(void)
 
 
 #if defined(CONFIG_440)
-static int do_chip_reset(unsigned long sys0, unsigned long sys1);
+static int do_chip_reset (unsigned long sys0, unsigned long sys1)
+{
+	/* Changes to cpc0_sys0 and cpc0_sys1 require chip
+	 * reset.
+	 */
+	mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000);	/* Set SWE */
+	mtdcr (cpc0_sys0, sys0);
+	mtdcr (cpc0_sys1, sys1);
+	mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000);	/* Clr SWE */
+	mtspr (dbcr0, 0x20000000);	/* Reset the chip */
+
+	return 1;
+}
 #endif
 
 
@@ -233,19 +289,33 @@ int checkcpu (void)
 #if !defined(CONFIG_IOP480)
 	char addstr[64] = "";
 	sys_info_t sys_info;
+	int cpu_num;
 
-	puts ("CPU:   ");
+	cpu_num = get_cpu_num();
+	if (cpu_num >= 0)
+		printf("CPU%d:  ", cpu_num);
+	else
+		puts("CPU:   ");
 
 	get_sys_info(&sys_info);
 
+#if defined(CONFIG_XILINX_440)
+	puts("IBM PowerPC 4");
+#else
 	puts("AMCC PowerPC 4");
+#endif
 
 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
-    defined(CONFIG_405EP) || defined(CONFIG_405EZ)
+    defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
+    defined(CONFIG_405EX)
 	puts("05");
 #endif
 #if defined(CONFIG_440)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	puts("60");
+#else
 	puts("40");
+#endif
 #endif
 
 	switch (pvr) {
@@ -293,6 +363,46 @@ int checkcpu (void)
 		puts("EZ Rev. A");
 		break;
 
+	case PVR_405EX1_RA:
+		puts("EX Rev. A");
+		strcpy(addstr, "Security support");
+		break;
+
+	case PVR_405EX2_RA:
+		puts("EX Rev. A");
+		strcpy(addstr, "No Security support");
+		break;
+
+	case PVR_405EXR1_RA:
+		puts("EXr Rev. A");
+		strcpy(addstr, "Security support");
+		break;
+
+	case PVR_405EXR2_RA:
+		puts("EXr Rev. A");
+		strcpy(addstr, "No Security support");
+		break;
+
+	case PVR_405EX1_RC:
+		puts("EX Rev. C");
+		strcpy(addstr, "Security support");
+		break;
+
+	case PVR_405EX2_RC:
+		puts("EX Rev. C");
+		strcpy(addstr, "No Security support");
+		break;
+
+	case PVR_405EXR1_RC:
+		puts("EXr Rev. C");
+		strcpy(addstr, "Security support");
+		break;
+
+	case PVR_405EXR2_RC:
+		puts("EXr Rev. C");
+		strcpy(addstr, "No Security support");
+		break;
+
 #if defined(CONFIG_440)
 	case PVR_440GP_RB:
 		puts("GP Rev. B");
@@ -416,6 +526,50 @@ int checkcpu (void)
 		strcpy(addstr, "No RAID 6 support");
 		break;
 
+	case PVR_460EX_RA:
+		puts("EX Rev. A");
+		strcpy(addstr, "No Security/Kasumi support");
+		break;
+
+	case PVR_460EX_SE_RA:
+		puts("EX Rev. A");
+		strcpy(addstr, "Security/Kasumi support");
+		break;
+
+	case PVR_460GT_RA:
+		puts("GT Rev. A");
+		strcpy(addstr, "No Security/Kasumi support");
+		break;
+
+	case PVR_460GT_SE_RA:
+		puts("GT Rev. A");
+		strcpy(addstr, "Security/Kasumi support");
+		break;
+
+	case PVR_460SX_RA:
+		puts("SX Rev. A");
+		strcpy(addstr, "Security support");
+		break;
+
+	case PVR_460SX_RA_V1:
+		puts("SX Rev. A");
+		strcpy(addstr, "No Security support");
+		break;
+
+	case PVR_460GX_RA:
+		puts("GX Rev. A");
+		strcpy(addstr, "Security support");
+		break;
+
+	case PVR_460GX_RA_V1:
+		puts("GX Rev. A");
+		strcpy(addstr, "No Security support");
+		break;
+
+	case PVR_VIRTEX5:
+		puts("x5 VIRTEX5");
+		break;
+
 	default:
 		printf (" UNKNOWN (PVR=%08x)", pvr);
 		break;
@@ -424,7 +578,7 @@ int checkcpu (void)
 	printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
 		sys_info.freqPLB / 1000000,
 		get_OPB_freq() / 1000000,
-		FREQ_EBC / 1000000);
+		sys_info.freqEBC / 1000000);
 
 	if (addstr[0] != 0)
 		printf("       %s\n", addstr);
@@ -434,14 +588,18 @@ int checkcpu (void)
 #endif	/* I2C_BOOTROM */
 #if defined(SDR0_PINSTP_SHIFT)
 	printf ("       Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
-	printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
+	printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
+#ifdef CONFIG_NAND_U_BOOT
+	puts(", booting from NAND");
+#endif /* CONFIG_NAND_U_BOOT */
+	putc('\n');
 #endif	/* SDR0_PINSTP_SHIFT */
 
-#if defined(CONFIG_PCI)
+#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
 	printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
 #endif
 
-#if defined(PCI_ASYNC)
+#if defined(CONFIG_PCI) && defined(PCI_ASYNC)
 	if (pci_async_enabled()) {
 		printf (", PCI async ext clock used");
 	} else {
@@ -450,11 +608,11 @@ int checkcpu (void)
 	}
 #endif
 
-#if defined(CONFIG_PCI)
+#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
 	putc('\n');
 #endif
 
-#if defined(CONFIG_405EP) || defined(CONFIG_405EZ)
+#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
 	printf ("       16 kB I-Cache 16 kB D-Cache");
 #elif defined(CONFIG_440)
 	printf ("       32 kB I-Cache 32 kB D-Cache");
@@ -478,7 +636,6 @@ int checkcpu (void)
 	return 0;
 }
 
-#if defined (CONFIG_440SPE)
 int ppc440spe_revB() {
 	unsigned int pvr;
 
@@ -488,7 +645,6 @@ int ppc440spe_revB() {
 	else
 		return 0;
 }
-#endif
 
 /* ------------------------------------------------------------------------- */
 
@@ -497,35 +653,19 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #if defined(CONFIG_BOARD_RESET)
 	board_reset();
 #else
-#if defined(CFG_4xx_RESET_TYPE)
-	mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
+#if defined(CONFIG_SYS_4xx_RESET_TYPE)
+	mtspr(dbcr0, CONFIG_SYS_4xx_RESET_TYPE << 28);
 #else
 	/*
 	 * Initiate system reset in debug control register DBCR
 	 */
 	mtspr(dbcr0, 0x30000000);
-#endif /* defined(CFG_4xx_RESET_TYPE) */
+#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
 #endif /* defined(CONFIG_BOARD_RESET) */
 
 	return 1;
 }
 
-#if defined(CONFIG_440)
-static int do_chip_reset (unsigned long sys0, unsigned long sys1)
-{
-	/* Changes to cpc0_sys0 and cpc0_sys1 require chip
-	 * reset.
-	 */
-	mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000);	/* Set SWE */
-	mtdcr (cpc0_sys0, sys0);
-	mtdcr (cpc0_sys1, sys1);
-	mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000);	/* Clr SWE */
-	mtspr (dbcr0, 0x20000000);	/* Reset the chip */
-
-	return 1;
-}
-#endif
-
 
 /*
  * Get timebase clock frequency
@@ -545,16 +685,14 @@ unsigned long get_tbclk (void)
 
 
 #if defined(CONFIG_WATCHDOG)
-void
-watchdog_reset(void)
+void watchdog_reset(void)
 {
 	int re_enable = disable_interrupts();
 	reset_4xx_watchdog();
 	if (re_enable) enable_interrupts();
 }
 
-void
-reset_4xx_watchdog(void)
+void reset_4xx_watchdog(void)
 {
 	/*
 	 * Clear TSR(WIS) bit
@@ -562,3 +700,15 @@ reset_4xx_watchdog(void)
 	mtspr(tsr, 0x40000000);
 }
 #endif	/* CONFIG_WATCHDOG */
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_PPC4xx_EMAC)
+	ppc_4xx_eth_initialize(bis);
+#endif
+	return 0;
+}