X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fppc4xx%2Fcpu_init.c;h=42eabfe568a5b6b0d48a5ebb8eb9bf435dcfe1f3;hb=f060054dadbbe7027ca088eed806a3ef1f82fdb7;hp=ae245910872e9e6f212683d0fbe200da91ffdf90;hpb=b78bb469f536b357ee21c54f40201dbe4b201ac3;p=u-boot

diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index ae24591087..42eabfe568 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2006
+ * (C) Copyright 2000-2007
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -25,6 +25,7 @@
 #include <watchdog.h>
 #include <ppc4xx_enet.h>
 #include <asm/processor.h>
+#include <asm/gpio.h>
 #include <ppc4xx.h>
 
 #if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
@@ -98,122 +99,107 @@ DECLARE_GLOBAL_DATA_PTR;
 # endif
 #endif /* CFG_INIT_DCACHE_CS */
 
-#if defined(CFG_440_GPIO_TABLE)
-gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
+#ifndef CFG_PLL_RECONFIG
+#define CFG_PLL_RECONFIG	0
+#endif
 
-void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_MAX])
+void reconfigure_pll(u32 new_cpu_freq)
 {
-	unsigned char i=0, j=0, reg_offset = 0, gpio_core;
-	unsigned long gpio_reg, gpio_core_add;
-
-	for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
-		j = 0;
-		reg_offset = 0;
-		/* GPIO config of the GPIOs 0 to 31 */
-		for (i=0; i<GPIO_MAX; i++, j++) {
-			if (i == GPIO_MAX/2) {
-				reg_offset = 4;
-				j = i-16;
-			}
-
-			gpio_core_add = (*gpio_tab)[gpio_core][i].add;
-
-			if (((*gpio_tab)[gpio_core][i].in_out == GPIO_IN) ||
-			     ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
-
-				switch ((*gpio_tab)[gpio_core][i].alt_nb) {
-				case GPIO_SEL:
-					break;
-
-				case GPIO_ALT1:
-					gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset))
-						& ~(GPIO_MASK >> (j*2));
-					gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
-					out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
-					break;
-
-				case GPIO_ALT2:
-					gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset))
-						& ~(GPIO_MASK >> (j*2));
-					gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
-					out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
-					break;
-
-				case GPIO_ALT3:
-					gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset))
-						& ~(GPIO_MASK >> (j*2));
-					gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
-					out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
-					break;
-				}
-			}
-
-			if (((*gpio_tab)[gpio_core][i].in_out == GPIO_OUT) ||
-			     ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
-
-				switch ((*gpio_tab)[gpio_core][i].alt_nb) {
-				case GPIO_SEL:
-					if (gpio_core == GPIO0) {
-						gpio_reg = in32(GPIO0_TCR) | (0x80000000 >> (j));
-						out32(GPIO0_TCR, gpio_reg);
-					}
-
-					if (gpio_core == GPIO1) {
-						gpio_reg = in32(GPIO1_TCR) | (0x80000000 >> (j));
-						out32(GPIO1_TCR, gpio_reg);
-					}
-
-					gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
-						& ~(GPIO_MASK >> (j*2));
-					out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
-					gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
-						& ~(GPIO_MASK >> (j*2));
-					out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
-					break;
-
-				case GPIO_ALT1:
-					gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
-						& ~(GPIO_MASK >> (j*2));
-					gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
-					out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
-					gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
-						& ~(GPIO_MASK >> (j*2));
-					gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
-					out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
-					break;
-
-				case GPIO_ALT2:
-					gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
-						& ~(GPIO_MASK >> (j*2));
-					gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
-					out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
-					gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
-						& ~(GPIO_MASK >> (j*2));
-					gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
-					out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
-					break;
-
-				case GPIO_ALT3:
-					gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
-						& ~(GPIO_MASK >> (j*2));
-					gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
-					out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
-					gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
-						& ~(GPIO_MASK >> (j*2));
-					gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
-					out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
-					break;
-				}
-			}
+#if defined(CONFIG_440EPX)
+	int	reset_needed = 0;
+	u32	reg, temp;
+	u32	prbdv0, target_prbdv0,				/* CLK_PRIMBD */
+		fwdva, target_fwdva, fwdvb, target_fwdvb,	/* CLK_PLLD */
+		fbdv, target_fbdv, lfbdv, target_lfbdv,
+		perdv0,	target_perdv0,				/* CLK_PERD */
+		spcid0,	target_spcid0;				/* CLK_SPCID */
+
+	/* Reconfigure clocks if necessary.
+	 * See PPC440EPx User's Manual, sections 8.2 and 14 */
+	if (new_cpu_freq == 667) {
+		target_prbdv0 = 2;
+		target_fwdva = 2;
+		target_fwdvb = 4;
+		target_fbdv = 20;
+		target_lfbdv = 1;
+		target_perdv0 = 4;
+		target_spcid0 = 4;
+
+		mfcpr(clk_primbd, reg);
+		temp = (reg & PRBDV_MASK) >> 24;
+		prbdv0 = temp ? temp : 8;
+		if (prbdv0 != target_prbdv0) {
+			reg &= ~PRBDV_MASK;
+			reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
+			mtcpr(clk_primbd, reg);
+			reset_needed = 1;
+		}
+
+		mfcpr(clk_plld, reg);
+
+		temp = (reg & PLLD_FWDVA_MASK) >> 16;
+		fwdva = temp ? temp : 16;
+
+		temp = (reg & PLLD_FWDVB_MASK) >> 8;
+		fwdvb = temp ? temp : 8;
+
+		temp = (reg & PLLD_FBDV_MASK) >> 24;
+		fbdv = temp ? temp : 32;
+
+		temp = (reg & PLLD_LFBDV_MASK);
+		lfbdv = temp ? temp : 64;
+
+		if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) {
+			reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
+				 PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
+			reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) |
+				((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
+				((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
+				(target_lfbdv == 64 ? 0 : target_lfbdv);
+			mtcpr(clk_plld, reg);
+			reset_needed = 1;
+		}
+
+		mfcpr(clk_perd, reg);
+		perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
+		if (perdv0 != target_perdv0) {
+			reg &= ~CPR0_PERD_PERDV0_MASK;
+			reg |= (target_perdv0 << 24);
+			mtcpr(clk_perd, reg);
+			reset_needed = 1;
+		}
+
+		mfcpr(clk_spcid, reg);
+		temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
+		spcid0 = temp ? temp : 4;
+		if (spcid0 != target_spcid0) {
+			reg &= ~CPR0_SPCID_SPCIDV0_MASK;
+			reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
+			mtcpr(clk_spcid, reg);
+			reset_needed = 1;
 		}
+
+		/* Set reload inhibit so configuration will persist across
+		 * processor resets */
+		mfcpr(clk_icfg, reg);
+		reg &= ~CPR0_ICFG_RLI_MASK;
+		reg |= 1 << 31;
+		mtcpr(clk_icfg, reg);
+	}
+
+	/* Reset processor if configuration changed */
+	if (reset_needed) {
+		__asm__ __volatile__ ("sync; isync");
+		mtspr(dbcr0, 0x20000000);
 	}
+#endif
 }
-#endif /* CFG_440_GPIO_TABLE */
 
 /*
  * Breath some life into the CPU...
  *
- * Set up the memory map,
+ * Reconfigure PLL if necessary,
+ * set up the memory map,
  * initialize a bunch of registers
  */
 void
@@ -222,8 +208,9 @@ cpu_init_f (void)
 #if defined(CONFIG_WATCHDOG)
 	unsigned long val;
 #endif
+	reconfigure_pll(CFG_PLL_RECONFIG);
 
-#if defined(CONFIG_405EP)
+#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
 	/*
 	 * GPIO0 setup (select GPIO or alternate function)
 	 */
@@ -239,31 +226,45 @@ cpu_init_f (void)
 	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
 	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);	/* three-state select			*/
 	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
+#if defined(CFG_GPIO0_ISR2H)
+	out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H);
+	out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L);
+#endif
+#if defined (CFG_GPIO0_TCR)
 	out32(GPIO0_TCR, CFG_GPIO0_TCR);	/* enable output driver for outputs	*/
+#endif
+#endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */
 
+#if defined (CONFIG_405EP)
 	/*
 	 * Set EMAC noise filter bits
 	 */
 	mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
+
+	/*
+	 * Enable the internal PCI arbiter
+	 */
+	mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
 #endif /* CONFIG_405EP */
 
-#if defined(CFG_440_GPIO_TABLE)
-	set_chip_gpio_configuration(&gpio_tab);
-#endif /* CFG_440_GPIO_TABLE */
+#if defined(CFG_4xx_GPIO_TABLE)
+	gpio_set_chip_configuration();
+#endif /* CFG_4xx_GPIO_TABLE */
 
 	/*
 	 * External Bus Controller (EBC) Setup
 	 */
 #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
 #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
-     defined(CONFIG_405EP) || defined(CONFIG_405))
+     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
+     defined(CONFIG_405EX) || defined(CONFIG_405))
 	/*
 	 * Move the next instructions into icache, since these modify the flash
 	 * we are running from!
 	 */
 	asm volatile("	bl	0f"		::: "lr");
 	asm volatile("0:	mflr	3"		::: "r3");
-	asm volatile("	addi 	4, 0, 14"	::: "r4");
+	asm volatile("	addi	4, 0, 14"	::: "r4");
 	asm volatile("	mtctr	4"		::: "ctr");
 	asm volatile("1:	icbt	0, 3");
 	asm volatile("	addi	3, 3, 32"	::: "r3");
@@ -314,13 +315,15 @@ cpu_init_f (void)
 #endif
 
 #if defined (CFG_EBC_CFG)
-	mtebc(epcr, CFG_EBC_CFG);
+	mtebc(EBC0_CFG, CFG_EBC_CFG);
 #endif
 
 #if defined(CONFIG_WATCHDOG)
 	val = mfspr(tcr);
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 	val |= 0xb8000000;      /* generate system reset after 1.34 seconds */
+#elif defined(CONFIG_440EPX)
+	val |= 0xb0000000;      /* generate system reset after 1.34 seconds */
 #else
 	val |= 0xf0000000;      /* generate system reset after 2.684 seconds */
 #endif
@@ -397,5 +400,6 @@ int cpu_init_r (void)
 	}
 #endif  /* defined(CONFIG_405GP) */
 #endif  /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */
+
 	return (0);
 }