X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fppc4xx%2Ffdt.c;h=c55e1cfbb72f94da0838fac7f341ba19d51b3a8c;hb=d4bade8d77aa20e2846fa4accff0e7fa7961a134;hp=ccc73d5d64e6d6de50bfe98d9dc56cd759252ad6;hpb=cb5d88b9611e0c35c53543ad3b4ab99fa82203e3;p=u-boot

diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c
index ccc73d5d64..c55e1cfbb7 100644
--- a/cpu/ppc4xx/fdt.c
+++ b/cpu/ppc4xx/fdt.c
@@ -37,21 +37,40 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void __ft_board_setup(void *blob, bd_t *bd)
 {
-	u32 val[4];
 	int rc;
+	int i;
+	u32 bxcr;
+	u32 ranges[EBC_NUM_BANKS * 4];
+	u32 *p = ranges;
+	char *ebc_path = "/plb/opb/ebc";
 
 	ft_cpu_setup(blob, bd);
 
-	/* Fixup NOR mapping */
-	val[0] = 0;				/* chip select number */
-	val[1] = 0;				/* always 0 */
-	val[2] = gd->bd->bi_flashstart;
-	val[3] = gd->bd->bi_flashsize;
-	rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
-				  val, sizeof(val), 1);
-	if (rc)
-		printf("Unable to update property NOR mapping, err=%s\n",
+	/*
+	 * Read 4xx EBC bus bridge registers to get mappings of the
+	 * peripheral banks into the OPB/PLB address space
+	 */
+	for (i = 0; i < EBC_NUM_BANKS; i++) {
+		mtdcr(ebccfga, EBC_BXCR(i));
+		bxcr = mfdcr(ebccfgd);
+
+		if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
+			*p++ = i;
+			*p++ = 0;
+			*p++ = bxcr & EBC_BXCR_BAS_MASK;
+			*p++ = EBC_BXCR_BANK_SIZE(bxcr);
+		}
+	}
+
+	/* Some 405 PPC's have EBC as direct PLB child in the dts */
+	if (fdt_path_offset(blob, "/plb/opb/ebc") < 0)
+		strcpy(ebc_path, "/plb/ebc");
+	rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
+				  (p - ranges) * sizeof(u32), 1);
+	if (rc) {
+		printf("Unable to update property EBC mappings, err=%s\n",
 		       fdt_strerror(rc));
+	}
 }
 void ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup")));
 
@@ -122,7 +141,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	 * Fixup all ethernet nodes
 	 * Note: aliases in the dts are required for this
 	 */
-	fdt_fixup_ethernet(blob, bd);
+	fdt_fixup_ethernet(blob);
 
 	/*
 	 * Fixup all available PCIe nodes by setting the device_type property