X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fppc4xx%2Ftlb.c;h=f44822dbab0dcfddbf4b4ce5ac34e65fa47b8258;hb=f060054dadbbe7027ca088eed806a3ef1f82fdb7;hp=2bfcba19bdbaf500a1d92496b0382eb32c778020;hpb=27f33e9f45ef7f9685cbdc65066a1828e85dde4f;p=u-boot

diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c
index 2bfcba19bd..f44822dbab 100644
--- a/cpu/ppc4xx/tlb.c
+++ b/cpu/ppc4xx/tlb.c
@@ -149,7 +149,9 @@ void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value)
 			/*
 			 * Now check the end-address if it's in the range
 			 */
-			if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) {
+			if (((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) ||
+			    ((tlb_vaddr < (vaddr + size - 1)) &&
+			     ((tlb_vaddr + tlb_size - 1) > (vaddr + size - 1)))) {
 				/*
 				 * Found a TLB in the range.
 				 * Change cache attribute in tlb2 word.