X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fpxa%2Fstart.S;h=23005e20f97af1884aa55da7a54b20fbc58f23bc;hb=79d14faf5471b7fdc4244cb6299e94e8170d826e;hp=d74f41ff383d822e67c67a5b38c34c124a8f6b25;hpb=a1191902cab72b9f7127365fac39a1e1d5c9abda;p=u-boot diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S index d74f41ff38..23005e20f9 100644 --- a/cpu/pxa/start.S +++ b/cpu/pxa/start.S @@ -6,8 +6,8 @@ * Copyright (C) 2000 Wolfgang Denk * Copyright (C) 2001 Alex Zuepke * Copyright (C) 2002 Kyle Harris - * Copyright (C) 2003 Robert Schwebel - * Copyright (C) 2003 Kai-Uwe Bloem + * Copyright (C) 2003 Robert Schwebel + * Copyright (C) 2003 Kai-Uwe Bloem * * See file CREDITS for list of people who contributed to this * project. @@ -30,6 +30,7 @@ #include #include +#include .globl _start _start: b reset @@ -56,7 +57,7 @@ _fiq: .word fiq * Startup Code (reset vector) * * do important init only if we don't start from RAM! - * - relocate armboot to ram + * - relocate armboot to RAM * - setup stack * - jump to second stage */ @@ -89,7 +90,7 @@ IRQ_STACK_START: .globl FIQ_STACK_START FIQ_STACK_START: .word 0x0badc0de -#endif +#endif /* CONFIG_USE_IRQ */ /****************************************************************************/ @@ -99,52 +100,54 @@ FIQ_STACK_START: /****************************************************************************/ reset: - mrs r0,cpsr /* set the cpu to SVC32 mode */ + mrs r0,cpsr /* set the CPU to SVC32 mode */ bic r0,r0,#0x1f /* (superviser mode, M=10011) */ orr r0,r0,#0x13 msr cpsr,r0 /* * we do sys-critical inits only at reboot, - * not when booting from ram! + * not when booting from RAM! */ -#ifdef CONFIG_INIT_CRITICAL +#ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit /* we do sys-critical inits */ -#endif +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ +#ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup ldr r2, _armboot_start ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ + cmp r0, r2 /* until source end address [r2] */ ble copy_loop +#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */ /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif +#endif /* CONFIG_USE_IRQ */ sub sp, r0, #12 /* leave 3 words for abort-stack */ clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 ble clbss_l @@ -162,8 +165,16 @@ _start_armboot: .word start_armboot /* - setup memory timing */ /* */ /****************************************************************************/ - -/* Interrupt-Controller base address */ +/* mk@tbd: Fix this! */ +#undef RCSR +#undef ICMR +#undef OSMR3 +#undef OSCR +#undef OWER +#undef OIER +#undef CCCR + +/* Interrupt-Controller base address */ IC_BASE: .word 0x40d00000 #define ICMR 0x04 @@ -178,34 +189,66 @@ OSTIMER_BASE: .word 0x40a00000 #define OWER 0x18 #define OIER 0x1C -/* Clock Manager Registers */ +/* Clock Manager Registers */ +#ifdef CONFIG_CPU_MONAHANS +# ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO +# error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!" +# endif /* !CFG_MONAHANS_RUN_MODE_OSC_RATIO */ +# ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO +# define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1 +# endif /* !CFG_MONAHANS_TURBO_RUN_MODE_RATIO */ +#else /* !CONFIG_CPU_MONAHANS */ #ifdef CFG_CPUSPEED CC_BASE: .word 0x41300000 #define CCCR 0x00 cpuspeed: .word CFG_CPUSPEED -#else +#else /* !CFG_CPUSPEED */ #error "You have to define CFG_CPUSPEED!!" -#endif - +#endif /* CFG_CPUSPEED */ +#endif /* CONFIG_CPU_MONAHANS */ - /* RS: ??? */ - .macro CPWAIT - mrc p15,0,r0,c2,c0,0 - mov r0,r0 + /* takes care the CP15 update has taken place */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg sub pc,pc,#4 .endm - cpu_init_crit: /* mask all IRQs */ +#ifndef CONFIG_CPU_MONAHANS ldr r0, IC_BASE mov r1, #0x00 str r1, [r0, #ICMR] - -#if defined(CFG_CPUSPEED) +#else /* CONFIG_CPU_MONAHANS */ + /* Step 1 - Enable CP6 permission */ + mrc p15, 0, r1, c15, c1, 0 @ read CPAR + orr r1, r1, #0x40 + mcr p15, 0, r1, c15, c1, 0 + CPWAIT r1 + + /* Step 2 - Mask ICMR & ICMR2 */ + mov r1, #0 + mcr p6, 0, r1, c1, c0, 0 @ ICMR + mcr p6, 0, r1, c7, c0, 0 @ ICMR2 + + /* turn off all clocks but the ones we will definitly require */ + ldr r1, =CKENA + ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC) + str r2, [r1] + ldr r1, =CKENB + ldr r2, =(CKENB_6_IRQ) + str r2, [r1] +#endif /* !CONFIG_CPU_MONAHANS */ /* set clock speed */ +#ifdef CONFIG_CPU_MONAHANS + ldr r0, =ACCR + ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK)) + str r1, [r0] +#else /* !CONFIG_CPU_MONAHANS */ +#ifdef CFG_CPUSPEED ldr r0, CC_BASE ldr r1, cpuspeed str r1, [r0, #CCCR] @@ -213,31 +256,35 @@ cpu_init_crit: mcr p14, 0, r0, c6, c0, 0 setspeed_done: -#endif + +#endif /* CFG_CPUSPEED */ +#endif /* CONFIG_CPU_MONAHANS */ /* * before relocating, we have to setup RAM timing * because memory timing is board-dependend, you will - * find a memsetup.S in your board directory. + * find a lowlevel_init.S in your board directory. */ mov ip, lr - bl memsetup + bl lowlevel_init mov lr, ip /* Memory interfaces are working. Disable MMU and enable I-cache. */ + /* mk: hmm, this is not in the monahans docs, leave it now but + * check here if it doesn't work :-) */ ldr r0, =0x2001 /* enable access to all coproc. */ mcr p15, 0, r0, c15, c1, 0 - CPWAIT + CPWAIT r0 mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */ - CPWAIT + CPWAIT r0 mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */ - CPWAIT + CPWAIT r0 mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */ - CPWAIT + CPWAIT r0 /* Enable the Icache */ /* @@ -290,7 +337,7 @@ setspeed_done: ldr r2, _armboot_start sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ @@ -400,7 +447,7 @@ fiq: bl do_fiq /* effiction fiq_save_user_regs */ irq_restore_user_regs -#else +#else /* !CONFIG_USE_IRQ */ .align 5 irq: @@ -414,20 +461,20 @@ fiq: bad_save_user_regs bl do_fiq -#endif +#endif /* CONFIG_USE_IRQ */ /****************************************************************************/ -/* */ +/* */ /* Reset function: the PXA250 doesn't have a reset function, so we have to */ -/* perform a watchdog timeout for a soft reset. */ -/* */ +/* perform a watchdog timeout for a soft reset. */ +/* */ /****************************************************************************/ .align 5 .globl reset_cpu - /* FIXME: this code is PXA250 specific. How is this handled on */ - /* other XScale processors? */ + /* FIXME: this code is PXA250 specific. How is this handled on */ + /* other XScale processors? */ reset_cpu: @@ -435,13 +482,13 @@ reset_cpu: ldr r0, OSTIMER_BASE ldr r1, [r0, #OWER] - orr r1, r1, #0x0001 /* bit0: WME */ + orr r1, r1, #0x0001 /* bit0: WME */ str r1, [r0, #OWER] /* OS timer does only wrap every 1165 seconds, so we have to set */ - /* the match register as well. */ + /* the match register as well. */ - ldr r1, [r0, #OSCR] /* read OS timer */ + ldr r1, [r0, #OSCR] /* read OS timer */ add r1, r1, #0x800 /* let OSMR3 match after */ add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */ str r1, [r0, #OSMR3]