X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fpxa%2Fusb.c;h=bd718a6fff8e7c5e85eb3c194d2cb1b9e3038ab9;hb=52cb4d4fb3487313f5a72ea740f527a4aefaa365;hp=5d273cb35186829954618324df6d8c7ec482b037;hpb=83dc830b1693252d996bda920cd5f3161d7c64a9;p=u-boot

diff --git a/cpu/pxa/usb.c b/cpu/pxa/usb.c
index 5d273cb351..bd718a6fff 100644
--- a/cpu/pxa/usb.c
+++ b/cpu/pxa/usb.c
@@ -23,23 +23,27 @@
 
 #include <common.h>
 
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
-# ifdef CONFIG_CPU_MONAHANS
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
+# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
 
 #include <asm/arch/pxa-regs.h>
+#include <usb.h>
 
-int usb_cpu_init()
+int usb_cpu_init(void)
 {
+#if defined(CONFIG_CPU_MONAHANS)
 	/* Enable USB host clock. */
 	CKENA |= (CKENA_2_USBHOST |  CKENA_20_UDC);
 	udelay(100);
+#endif
+#if defined(CONFIG_PXA27X)
+	/* Enable USB host clock. */
+	CKEN |= CKEN10_USBHOST;
+#endif
 
+#if defined(CONFIG_CPU_MONAHANS)
 	/* Configure Port 2 for Host (USB Client Registers) */
 	UP2OCR = 0x3000c;
-
-#if 0
-	GPIO2_2 = 0x801; /* USBHPEN - Alt. Fkt. 1 */
-	GPIO3_2 = 0x801; /* USBHPWR - Alt. Fkt. 1 */
 #endif
 
 	UHCHR |= UHCHR_FHR;
@@ -50,29 +54,59 @@ int usb_cpu_init()
 	while (UHCHR & UHCHR_FSBIR)
 		udelay(1);
 
-#if 0
-	UHCHR |= UHCHR_PCPL; /* USBHPEN is active low */
-	UHCHR |= UHCHR_PSPL; /* USBHPWR is active low */
-#endif
-
+#if defined(CONFIG_CPU_MONAHANS)
 	UHCHR &= ~UHCHR_SSEP0;
+#endif
+#if defined(CONFIG_PXA27X)
+	UHCHR &= ~UHCHR_SSEP2;
+#endif
 	UHCHR &= ~UHCHR_SSEP1;
 	UHCHR &= ~UHCHR_SSE;
 
 	return 0;
 }
 
-int usb_cpu_stop()
+int usb_cpu_stop(void)
 {
-	/* may not want to do this */
-	/* CKENA &= ~(CKENA_2_USBHOST |  CKENA_20_UDC); */
+	UHCHR |= UHCHR_FHR;
+	udelay(11);
+	UHCHR &= ~UHCHR_FHR;
+
+	UHCCOMS |= 1;
+	udelay(10);
+
+#if defined(CONFIG_CPU_MONAHANS)
+	UHCHR |= UHCHR_SSEP0;
+#endif
+#if defined(CONFIG_PXA27X)
+	UHCHR |= UHCHR_SSEP2;
+#endif
+	UHCHR |= UHCHR_SSEP1;
+	UHCHR |= UHCHR_SSE;
+
 	return 0;
 }
 
-int usb_cpu_init_fail()
+int usb_cpu_init_fail(void)
 {
+	UHCHR |= UHCHR_FHR;
+	udelay(11);
+	UHCHR &= ~UHCHR_FHR;
+
+	UHCCOMS |= 1;
+	udelay(10);
+
+#if defined(CONFIG_CPU_MONAHANS)
+	UHCHR |= UHCHR_SSEP0;
+#endif
+#if defined(CONFIG_PXA27X)
+	UHCHR |= UHCHR_SSEP2;
+#endif
+	UHCHR |= UHCHR_SSEP1;
+	UHCHR |= UHCHR_SSE;
+
 	return 0;
 }
 
-# endif /* CONFIG_CPU_MONAHANS */
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
+# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */