X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fsa1100%2Fcpu.c;h=58e90dc9f69ec967e91675fd926d6f1ace7a1f10;hb=f666dea8ab215c76c3c2a077ad299f90dd1ace7c;hp=34adf91ad1ba647d65a37346a545ca78d8afe51d;hpb=f6e20fc6ca5a45316f94743d8b60dce4d9766bc8;p=u-boot

diff --git a/cpu/sa1100/cpu.c b/cpu/sa1100/cpu.c
index 34adf91ad1..58e90dc9f6 100644
--- a/cpu/sa1100/cpu.c
+++ b/cpu/sa1100/cpu.c
@@ -32,20 +32,13 @@
 
 #include <common.h>
 #include <command.h>
+#include <asm/system.h>
 
-int cpu_init (void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
 #ifdef CONFIG_USE_IRQ
-	DECLARE_GLOBAL_DATA_PTR;
-
-	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+DECLARE_GLOBAL_DATA_PTR;
 #endif
-	return 0;
-}
+
+static void cache_flush(void);
 
 int cleanup_before_linux (void)
 {
@@ -56,90 +49,22 @@ int cleanup_before_linux (void)
 	 * just disable everything that can disturb booting linux
 	 */
 
-	unsigned long i;
-
 	disable_interrupts ();
 
 	/* turn off I-cache */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~0x1000;
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	icache_disable();
+	dcache_disable();
 
 	/* flush I-cache */
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-
-	return (0);
-}
-
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	extern void reset_cpu (ulong addr);
-
-	printf ("resetting ...\n");
-
-	udelay (50000);				/* wait 50 ms */
-	disable_interrupts ();
-	reset_cpu (0);
+	cache_flush();
 
-	/*NOTREACHED*/
 	return (0);
 }
 
-/* taken from blob */
-void icache_enable (void)
+/* flush I/D-cache */
+static void cache_flush (void)
 {
-	register u32 i;
-
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
-	/* set i-cache */
-	i |= 0x1000;
-
-	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
+	unsigned long i = 0;
 
-void icache_disable (void)
-{
-	register u32 i;
-
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
-	/* clear i-cache */
-	i &= ~0x1000;
-
-	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-
-	/* flush i-cache */
 	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
 }
-
-int icache_status (void)
-{
-	register u32 i;
-
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
-	/* return bit */
-	return (i & 0x1000);
-}
-
-/* we will never enable dcache, because we have to setup MMU first */
-void dcache_enable (void)
-{
-	return;
-}
-
-void dcache_disable (void)
-{
-	return;
-}
-
-int dcache_status (void)
-{
-	return 0;					/* always off */
-}