X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=doc%2FREADME.fsl-ddr;h=3992640ba30546e3e3028b48b1fac8944b6c75e4;hb=bf36c5d521c17460553e39d82232a51273b83aed;hp=1d50153d58c2a4802f1b48fcd8f7291734f98cf5;hpb=e5a07171767115b446fb5070e9c0293fd1190c03;p=u-boot

diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index 1d50153d58..3992640ba3 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -1,5 +1,28 @@
-
-Table of interleaving modes supported in cpu/8xxx/ddr/
+Table of interleaving 2-4 controllers
+=====================================
+  +--------------+-----------------------------------------------------------+
+  |Configuration |                    Memory Controller                      |
+  |              |       1              2              3             4       |
+  |--------------+--------------+--------------+-----------------------------+
+  | Two memory   | Not Intlv'ed | Not Intlv'ed |                             |
+  | complexes    +--------------+--------------+                             |
+  |              |      2-way Intlv'ed         |                             |
+  |--------------+--------------+--------------+--------------+              |
+  |              | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |              |
+  | Three memory +--------------+--------------+--------------+              |
+  | complexes    |         2-way Intlv'ed      | Not Intlv'ed |              |
+  |              +-----------------------------+--------------+              |
+  |              |                  3-way Intlv'ed            |              |
+  +--------------+--------------+--------------+--------------+--------------+
+  |              | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |
+  | Four memory  +--------------+--------------+--------------+--------------+
+  | complexes    |       2-way Intlv'ed        |       2-way Intlv'ed        |
+  |              +-----------------------------+-----------------------------+
+  |              |                      4-way Intlv'ed                       |
+  +--------------+-----------------------------------------------------------+
+
+
+Table of 2-way interleaving modes supported in cpu/8xxx/ddr/
 ======================================================
   +-------------+---------------------------------------------------------+
   |		|		    Rank Interleaving			  |
@@ -56,6 +79,15 @@ The ways to configure the ddr interleaving mode
   # superbank
   setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
 
+  # 1KB 3-way interleaving
+  setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB"
+
+  # 4KB 3-way interleaving
+  setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB"
+
+  # 8KB 3-way interleaving
+  setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB"
+
   # disable bank (chip-select) interleaving
   setenv hwconfig "fsl_ddr:bank_intlv=null"
 
@@ -71,6 +103,11 @@ The ways to configure the ddr interleaving mode
   # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
   setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
 
+  # bank(chip-select) interleaving (auto)
+  setenv hwconfig "fsl_ddr:bank_intlv=auto"
+  This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings
+  on DIMMs.
+
 Memory controller address hashing
 ==================================
 If the DDR controller supports address hashing, it can be enabled by hwconfig.
@@ -250,7 +287,7 @@ print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
 	c<n>		- the controller number, eg. c0, c1
 	d<n>		- the DIMM number, eg. d0, d1
 	spd		- print SPD data
-	dimmparms	- DIMM paramaters, calcualted from SPD
+	dimmparms	- DIMM parameters, calculated from SPD
 	commonparms	- lowest common parameters for all DIMMs
 	opts		- options
 	addresses	- address assignment (not implemented yet)
@@ -260,7 +297,7 @@ edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value>
 	c<n>		- the controller number, eg. c0, c1
 	d<n>		- the DIMM number, eg. d0, d1
 	spd		- print SPD data
-	dimmparms	- DIMM paramaters, calcualted from SPD
+	dimmparms	- DIMM parameters, calculated from SPD
 	commonparms	- lowest common parameters for all DIMMs
 	opts		- options
 	addresses	- address assignment (not implemented yet)