X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=doc%2FREADME.fsl-ddr;h=3992640ba30546e3e3028b48b1fac8944b6c75e4;hb=bf36c5d521c17460553e39d82232a51273b83aed;hp=f94b56f628cc369a7927a3a683bdf405363a0767;hpb=1c27059a2f7158a9c9a8778535b030935d75179d;p=u-boot

diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index f94b56f628..3992640ba3 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -103,6 +103,11 @@ The ways to configure the ddr interleaving mode
   # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
   setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
 
+  # bank(chip-select) interleaving (auto)
+  setenv hwconfig "fsl_ddr:bank_intlv=auto"
+  This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings
+  on DIMMs.
+
 Memory controller address hashing
 ==================================
 If the DDR controller supports address hashing, it can be enabled by hwconfig.