X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=doc%2FREADME.fsl-esdhc;h=29cc6619eaba7a5caaee80709f04897a6030ceca;hb=f717b4c8e7fc871573755a05be96c8ef857eabce;hp=7e713875763e4a5a86e4934c7c33bb7c4b406efd;hpb=d81572c272d4b0980fb9b8a02e1357090b002398;p=u-boot

diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc
index 7e71387576..29cc6619ea 100644
--- a/doc/README.fsl-esdhc
+++ b/doc/README.fsl-esdhc
@@ -20,5 +20,3 @@ Freescale esdhc-specific options
 	- CONFIG_SYS_FSL_ESDHC_BE
 		ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined
 		by ESDHC IP's endian mode or processor's endian mode.
-
-	- CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V.