X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=doc%2FREADME.imx5;h=c5312b69d3598907d803b2dae71157094389da83;hb=f82eb2fa5df86b7180ea355a3cb98482f7c27269;hp=e08941e2ae3c1282b4829399023bf9ddb3e5a3da;hpb=a098cf41fdb2a6607c675f7fe4f3164617c9367e;p=u-boot

diff --git a/doc/README.imx5 b/doc/README.imx5
index e08941e2ae..c5312b69d3 100644
--- a/doc/README.imx5
+++ b/doc/README.imx5
@@ -20,3 +20,9 @@ i.MX5x SoCs.
     This option should be enabled for boards having a SYS_ON_OFF_CTL signal
     connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
     reference designs.
+
+2. CONVENTIONS FOR FUSE ASSIGNMENTS
+-----------------------------------
+
+2.1 MAC Address: It is stored in the words 9 to 14 of fuse bank 1, using the
+    natural MAC byte order (i.e. MSB first).