X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=doc%2FREADME.imx5;h=ea0e144cedcf2074a4752e8d1f03a7b9681ae78b;hb=cccab03a529ac1bf1a66ff75fb15784005ec8570;hp=e08941e2ae3c1282b4829399023bf9ddb3e5a3da;hpb=b8a7c467960ffb4d5a5e1eef5f7783fb6f594542;p=u-boot

diff --git a/doc/README.imx5 b/doc/README.imx5
index e08941e2ae..ea0e144ced 100644
--- a/doc/README.imx5
+++ b/doc/README.imx5
@@ -20,3 +20,21 @@ i.MX5x SoCs.
     This option should be enabled for boards having a SYS_ON_OFF_CTL signal
     connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
     reference designs.
+
+2. CONVENTIONS FOR FUSE ASSIGNMENTS
+-----------------------------------
+
+2.1 MAC Address: It is stored in the words 9 to 14 of fuse bank 1, using the
+    natural MAC byte order (i.e. MSB first).
+
+    This is an example how to program an example MAC address 01:23:45:67:89:ab
+    into the eFuses. Assure that the programming voltage is available and then
+    execute:
+
+    => fuse prog -y 1 9 01 23 45 67 89 ab
+
+    After programming a MAC address, consider locking the MAC fuses. This is
+    done by programming the MAC_ADDR_LOCK fuse, which is bit 4 of word 0 in
+    bank 1:
+
+    => fuse prog -y 1 0 10