X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=doc%2FREADME.mpc85xx-spin-table;h=72c7bd7b5d7309d944b3acd0d29e093373772adc;hb=46abfcc99e04efa75ed293bd871092c31d0f3be3;hp=8da768a2a6c540c41c583cc68bc34bc37a413afe;hpb=f04821a8ca714459481bd9fd315af2b5f92d99a6;p=u-boot

diff --git a/doc/README.mpc85xx-spin-table b/doc/README.mpc85xx-spin-table
index 8da768a2a6..72c7bd7b5d 100644
--- a/doc/README.mpc85xx-spin-table
+++ b/doc/README.mpc85xx-spin-table
@@ -1,7 +1,7 @@
 Spin table in cache
 =====================================
 As specified by ePAPR v1.1, the spin table needs to be in cached memory. After
-DDR is initialized and U-boot relocates itself into DDR, the spin table is
+DDR is initialized and U-Boot relocates itself into DDR, the spin table is
 accessible for core 0. It is part of release.S, within 4KB range after
 __secondary_start_page. For other cores to use the spin table, the booting
 process is described below: