X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=doc%2FREADME.mpc85xxads;h=28bbcbe095dfa20b8af64369e47a5b6d667e69b2;hb=69a00875e3db178cfcb19ea8ab97c8927a11e593;hp=046f981cf0d299695e1d7835e64a3662fdeff44b;hpb=9d62f20d0861ef87460d073dc189c851715b46ae;p=u-boot

diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads
index 046f981cf0..28bbcbe095 100644
--- a/doc/README.mpc85xxads
+++ b/doc/README.mpc85xxads
@@ -35,7 +35,7 @@ Updated 13-July-2004 Jon Loeliger
     "On"  == 0
 
     SW18 is switch 18 as silk-screened onto the board.
-    SW4[8] is the bit labled 8 on Switch 4.
+    SW4[8] is the bit labeled 8 on Switch 4.
     SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2
     SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3
 
@@ -144,8 +144,8 @@ Updated 13-July-2004 Jon Loeliger
 			    also manual config the DDR after undef this
 			    definition.
     CONFIG_DDR_ECC	    only for ECC DDR module
-    CONFIG_DDR_DLL	    DLL fix on some ADS boards needed for more
-			    stability.
+    CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN	    DLL fix on some ADS boards needed
+			    for more stability.
     CONFIG_HAS_FEC	    If an FEC is on chip, set to 1, else 0.
 
 Other than the above definitions, the rest in the config files are