X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=doc%2FREADME.sbc8349;h=2c35919f28c81adc79c4b7bea6b00ff63ac4cad8;hb=f30c62bbe8988a8341970cbb7e14bb7a99abb157;hp=a0ac6388d6060e8653212304ae0e83843a68cdd4;hpb=f6d3faae792be848567688df7ea3f803c25af5b2;p=u-boot diff --git a/doc/README.sbc8349 b/doc/README.sbc8349 index a0ac6388d6..2c35919f28 100644 --- a/doc/README.sbc8349 +++ b/doc/README.sbc8349 @@ -21,15 +21,22 @@ Flash Details: The flash type is intel 28F640Jx (4096x16) [one device]. Base address is 0xFF80_0000 which is also where the Hardware Reset Configuration -Word (HRCW) is stored. Caution should be used to not overwrite the -HRCW, or "CF RCW" with a Wind River ICE will be required to restore -the HRCW and allow the board to enter background mode for further -steps in the flash process. +Word (HRCW) is stored. Caution should be used to not reset the +board without having a valid HRCW in place (i.e. erased flash) as +then a Wind River ICE will be required to restore the HRCW and flash +image. Restoring a corrupted or missing flash image: ============================================= +Note that U-boot versions up to and including 2009.06 had essentially +two copies of u-boot in flash; one at the very beginning, which set +the HRCW, and one at the very end, which was the image that was run. +As of this point in time, the two have been combined into just one +at the beginning of flash, which provides both the HRCW, and the image +that is executed. This frees up the remainder of flash for other uses. +Use of the u-boot command "fli" will indicate what parts are in use. Details for storing U-boot to flash using a Wind River ICE can be found on page 19 of the board manual (request ERG-00328-001). The following is a summary of that information: @@ -39,9 +46,9 @@ is a summary of that information: - Select the appropriate flash type (listed above) - Prepare a u-boot image by using the Wind River Convert utility; by using "Convert and Add file" on the ELF file from your build. - Convert from FFF0_0000 to FFFF_FFFF (or to FFF3_FFFF if you are - trying to preserve your old environment settings). - - Set the start address of the erase/flash process to FFF0_0000 + Convert from FF80_0000 to FFFF_FFFF (or to FF83_FFFF if you are + trying to preserve your old environment settings and user flash). + - Set the start address of the erase/flash process to FF80_0000 - Set the target RAM required to 64kB. - Select sectors for erasing (see note on enviroment below) - Select Erase and Reprogram. @@ -59,7 +66,7 @@ beginning with "SCGA TSEC1" and "SCGA TSEC2". This allows you to use all the remaining register file content. If you wish to preserve your prior U-Boot environment settings, -then convert (and erase to) 0xFFF3FFFF instead of 0xFFFFFFFF. +then convert (and erase to) 0xFF83FFFF instead of 0xFFFFFFFF. The size for converting (and erasing) must be at least as large as u-boot.bin. @@ -73,27 +80,48 @@ has been copied to the TFTP server, the commands are: tftp 200000 u-boot.bin protect off all - erase fff00000 fff3ffff - cp.b 200000 fff00000 3ffff + erase ff800000 ff83ffff + cp.b 200000 ff800000 40000 protect on all +You may wish to do a "md ff800000 20" operation as a prefix and postfix +to the above steps to inspect/compare the HRCW before/after as an extra +safety check before resetting the board upon completion of the reflash. PCI: ==== -This board and U-Boot have been tested with PCI built in, on a SBC8349 -and confirmed that the "pci" command showed the intel e1000 that was -present in the PCI slot. Note that if a 33MHz 32bit card is inserted -in the slot, then the whole board will clock down to a 33MHz base -clock instead of the default 66MHz. This will change the baud clocks -and mess up your serial console output. If you want to use a 33MHz PCI -card, then you should build a U-Boot with #undef PCI_66M in the -include/configs/sbc8349.h and store this to flash prior to powering down -the board and inserting the 33MHz PCI card. - -By default PCI support is disabled to better support very early -revision MPC834x chips with possible PCI issues. Also PCI support is -untested on the sbc8347 variants at this point in time. - - - Paul Gortmaker, 01/2007 +There are three configuration choices: + sbc8349_config + sbc8349_PCI_33_config + sbc8349_PCI_66_config + +The 1st does not enable CONFIG_PCI, and assumes that the PCI slot +will be left empty (M66EN high), and so the board will operate with +a base clock of 66MHz. Note that you need both PCI enabled in u-boot +and linux in order to have functional PCI under linux. The only +reason for choosing to not enable PCI would be if you had a very +early (rev 1.0) CPU with possible PCI issues. + +The second enables PCI support and builds for a 33MHz clock rate. Note +that if a 33MHz 32bit card is inserted in the slot, then the whole board +will clock down to a 33MHz base clock instead of the default 66MHz. This +will change the baud clocks and mess up your serial console output if you +were previously running at 66MHz. If you want to use a 33MHz PCI card, +then you should build a U-Boot with sbc8349_PCI_33_config and store this +to flash prior to powering down the board and inserting the 33MHz PCI +card. + +The third option builds PCI support in, and leaves the clocking at the +default 66MHz. This has been tested with an intel PCI-X e1000 card. +This is also the appropriate choice for people with a recent (non 1.0) +CPU who currently have the PCI slot physically empty, but intend to +possibly add a PCI-X card at a later date. + + => pci + Scanning PCI devices on bus 0 + BusDevFun VendorId DeviceId Device Class Sub-Class + _____________________________________________________________ + 00.00.00 0x1957 0x0080 Processor 0x20 + 00.11.00 0x8086 0x1026 Network controller 0x00 + =>