X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=doc%2FREADME.x86;h=c96a22cb08d8ba4a594c94a136285b5098b0029f;hb=0d7f1ae0fe6c0d9af2c0208aab4843ec3fdfaf52;hp=c542a6965c34b61883a57a31d8f1c9c84562fa6a;hpb=470135be276b2d92c6da464c68839202d4ff0d08;p=u-boot

diff --git a/doc/README.x86 b/doc/README.x86
index c542a6965c..c96a22cb08 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -26,6 +26,7 @@ In this case, known as bare mode, from the fact that it runs on the
 are supported:
 
    - Bayley Bay CRB
+   - Cherry Hill CRB
    - Congatec QEVAL 2.0 & conga-QA3/E3845
    - Cougar Canyon 2 CRB
    - Crown Bay CRB
@@ -332,6 +333,35 @@ the default value 0xfffc0000.
 
 ---
 
+Intel Cherry Hill specific instructions for bare mode:
+
+This uses Intel FSP for Braswell platform. Download it from Intel FSP website,
+put the .fd file to the board directory and rename it to fsp.bin.
+
+Extract descriptor.bin and me.bin from the original BIOS on the board using
+ifdtool and put them to the board directory as well.
+
+Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS
+image for the integrated graphics device. Instead a new binary called Video
+BIOS Table (VBT) is shipped. Put it to the board directory and rename it to
+vbt.bin if you want graphics support in U-Boot.
+
+Now you can build U-Boot and obtain u-boot.rom
+
+$ make cherryhill_defconfig
+$ make all
+
+An important note for programming u-boot.rom to the on-board SPI flash is that
+you need make sure the SPI flash's 'quad enable' bit in its status register
+matches the settings in the descriptor.bin, otherwise the board won't boot.
+
+For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the
+status register by DediProg in: Config > Modify Status Register > Write Status
+Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it
+persists in SPI flash part regardless of the u-boot.rom image burned.
+
+---
+
 Intel Galileo instructions for bare mode:
 
 Only one binary blob is needed for Remote Management Unit (RMU) within Intel