X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=doc%2FREADME.x86;h=c96a22cb08d8ba4a594c94a136285b5098b0029f;hb=0d7f1ae0fe6c0d9af2c0208aab4843ec3fdfaf52;hp=c69dc1c511341501d3a3e5c5ae904c2ee2e10fcb;hpb=fa8967cfbaed5582ba987756fa9f0470a9affbf4;p=u-boot

diff --git a/doc/README.x86 b/doc/README.x86
index c69dc1c511..c96a22cb08 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -18,12 +18,15 @@ U-Boot supports running as a coreboot [1] payload on x86. So far only Link
 work with minimal adjustments on other x86 boards since coreboot deals with
 most of the low-level details.
 
+U-Boot is a main bootloader on Intel Edison board.
+
 U-Boot also supports booting directly from x86 reset vector, without coreboot.
 In this case, known as bare mode, from the fact that it runs on the
 'bare metal', U-Boot acts like a BIOS replacement. The following platforms
 are supported:
 
    - Bayley Bay CRB
+   - Cherry Hill CRB
    - Congatec QEVAL 2.0 & conga-QA3/E3845
    - Cougar Canyon 2 CRB
    - Crown Bay CRB
@@ -61,6 +64,16 @@ Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
 to point to a new board. You can also change the Cache-As-RAM (CAR) related
 settings here if the default values do not fit your new board.
 
+Build Instructions for U-Boot as main bootloader
+------------------------------------------------
+
+Intel Edison instructions:
+
+Simple you can build U-Boot and obtain u-boot.bin
+
+$ make edison_defconfig
+$ make all
+
 Build Instructions for U-Boot as BIOS replacement (bare mode)
 -------------------------------------------------------------
 Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
@@ -320,6 +333,35 @@ the default value 0xfffc0000.
 
 ---
 
+Intel Cherry Hill specific instructions for bare mode:
+
+This uses Intel FSP for Braswell platform. Download it from Intel FSP website,
+put the .fd file to the board directory and rename it to fsp.bin.
+
+Extract descriptor.bin and me.bin from the original BIOS on the board using
+ifdtool and put them to the board directory as well.
+
+Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS
+image for the integrated graphics device. Instead a new binary called Video
+BIOS Table (VBT) is shipped. Put it to the board directory and rename it to
+vbt.bin if you want graphics support in U-Boot.
+
+Now you can build U-Boot and obtain u-boot.rom
+
+$ make cherryhill_defconfig
+$ make all
+
+An important note for programming u-boot.rom to the on-board SPI flash is that
+you need make sure the SPI flash's 'quad enable' bit in its status register
+matches the settings in the descriptor.bin, otherwise the board won't boot.
+
+For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the
+status register by DediProg in: Config > Modify Status Register > Write Status
+Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it
+persists in SPI flash part regardless of the u-boot.rom image burned.
+
+---
+
 Intel Galileo instructions for bare mode:
 
 Only one binary blob is needed for Remote Management Unit (RMU) within Intel
@@ -455,6 +497,33 @@ Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then,
 
 => zboot 01000000 - 04000000 1b1ab50
 
+Updating U-Boot on Edison
+-------------------------
+By default Intel Edison boards are shipped with preinstalled heavily
+patched U-Boot v2014.04. Though it supports DFU which we may be able to
+use.
+
+1. Prepare u-boot.bin as described in chapter above. You still need one
+more step (if and only if you have original U-Boot), i.e. run the
+following command:
+
+$ truncate -s %4096 u-boot.bin
+
+2. Run your board and interrupt booting to U-Boot console. In the console
+call:
+
+ => run do_force_flash_os
+
+3. Wait for few seconds, it will prepare environment variable and runs
+DFU. Run DFU command from the host system:
+
+$ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin
+
+4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and
+reset the board:
+
+ => reset
+
 CPU Microcode
 -------------
 Modern CPUs usually require a special bit stream called microcode [8] to be
@@ -753,11 +822,7 @@ command.
 You can also bake this behaviour into your build by hard-coding the
 environment variables if you add this to minnowmax.h:
 
-#undef CONFIG_BOOTARGS
 #undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_BOOTARGS		\
-	"root=/dev/sda2 ro"
 #define CONFIG_BOOTCOMMAND	\
 	"ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic; " \
 	"ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; " \
@@ -766,6 +831,10 @@ environment variables if you add this to minnowmax.h:
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS "boot=zboot 03000000 0 04000000 ${filesize}"
 
+and change CONFIG_BOOTARGS value in configs/minnowmax_defconfig to:
+
+CONFIG_BOOTARGS="root=/dev/sda2 ro"
+
 Test with SeaBIOS
 -----------------
 SeaBIOS [14] is an open source implementation of a 16-bit x86 BIOS. It can run