X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fblock%2Fahci.c;h=e64df4f98d6220acca20fb255115de756adf28f4;hb=13fbde6e4f600d94f0a1fb6ae49c6b4888033cec;hp=a05d9cfd766861cdcaabe8ed5f1ec8639d11a678;hpb=90b276f6a2a9e197eadce297fd593d85397bc430;p=u-boot diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index a05d9cfd76..e64df4f98d 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -3,26 +3,9 @@ * Author: Jason Jin * Zhang Wei * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ * * with the reference on libata and ahci drvier in kernel - * */ #include @@ -33,12 +16,14 @@ #include #include #include -#include +#include #include #include +static int ata_io_flush(u8 port); + struct ahci_probe_ent *probe_ent = NULL; -hd_driveid_t *ataid[AHCI_MAX_PORTS]; +u16 *ataid[AHCI_MAX_PORTS]; #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) @@ -52,6 +37,12 @@ hd_driveid_t *ataid[AHCI_MAX_PORTS]; #define MAX_SATA_BLOCKS_READ_WRITE 0x80 #endif +/* Maximum timeouts for each event */ +#define WAIT_MS_SPINUP 20000 +#define WAIT_MS_DATAIO 5000 +#define WAIT_MS_FLUSH 5000 +#define WAIT_MS_LINKUP 4 + static inline u32 ahci_port_base(u32 base, u32 port) { return base + 0x100 + (port * 0x80); @@ -116,6 +107,27 @@ static int waiting_for_cmd_completed(volatile u8 *offset, return (i < timeout_msec) ? 0 : -1; } +int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port) +{ + u32 tmp; + int j = 0; + u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; + + /* + * Bring up SATA link. + * SATA link bringup time is usually less than 1 ms; only very + * rarely has it taken between 1-2 ms. Never seen it above 2 ms. + */ + while (j < WAIT_MS_LINKUP) { + tmp = readl(port_mmio + PORT_SCR_STAT); + tmp &= PORT_SCR_STAT_DET_MASK; + if (tmp == PORT_SCR_STAT_DET_PHYRDY) + return 0; + udelay(1000); + j++; + } + return 1; +} static int ahci_host_init(struct ahci_probe_ent *probe_ent) { @@ -125,15 +137,16 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) unsigned short vendor; #endif volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; - u32 tmp, cap_save; - int i, j; + u32 tmp, cap_save, cmd; + int i, j, ret; volatile u8 *port_mmio; + u32 port_map; debug("ahci_host_init: start\n"); cap_save = readl(mmio + HOST_CAP); cap_save &= ((1 << 28) | (1 << 17)); - cap_save |= (1 << 27); + cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ /* global controller reset */ tmp = readl(mmio + HOST_CTL); @@ -169,6 +182,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) #endif probe_ent->cap = readl(mmio + HOST_CAP); probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); + port_map = probe_ent->port_map; probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; debug("cap 0x%x port_map 0x%x n_ports %d\n", @@ -178,6 +192,8 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID; for (i = 0; i < probe_ent->n_ports; i++) { + if (!(port_map & (1 << i))) + continue; probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); port_mmio = (u8 *) probe_ent->port[i].port_mmio; ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); @@ -197,18 +213,52 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) msleep(500); } - debug("Spinning up port %d... ", i); - writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); + /* Add the spinup command to whatever mode bits may + * already be on in the command register. + */ + cmd = readl(port_mmio + PORT_CMD); + cmd |= PORT_CMD_FIS_RX; + cmd |= PORT_CMD_SPIN_UP; + writel_with_flush(cmd, port_mmio + PORT_CMD); + + /* Bring up SATA link. */ + ret = ahci_link_up(probe_ent, i); + if (ret) { + printf("SATA link %d timeout.\n", i); + continue; + } else { + debug("SATA link ok.\n"); + } + + /* Clear error status */ + tmp = readl(port_mmio + PORT_SCR_ERR); + if (tmp) + writel(tmp, port_mmio + PORT_SCR_ERR); + + debug("Spinning up device on SATA port %d... ", i); j = 0; - while (j < 1000) { - tmp = readl(port_mmio + PORT_SCR_STAT); - if ((tmp & 0xf) == 0x3) + while (j < WAIT_MS_SPINUP) { + tmp = readl(port_mmio + PORT_TFDATA); + if (!(tmp & (ATA_BUSY | ATA_DRQ))) break; udelay(1000); + tmp = readl(port_mmio + PORT_SCR_STAT); + tmp &= PORT_SCR_STAT_DET_MASK; + if (tmp == PORT_SCR_STAT_DET_PHYRDY) + break; j++; } - if (j == 1000) + + tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK; + if (tmp == PORT_SCR_STAT_DET_COMINIT) { + debug("SATA link %d down (COMINIT received), retrying...\n", i); + i--; + continue; + } + + printf("Target spinup took %d ms.\n", j); + if (j == WAIT_MS_SPINUP) debug("timeout.\n"); else debug("ok.\n"); @@ -230,8 +280,8 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) /* register linkup ports */ tmp = readl(port_mmio + PORT_SCR_STAT); - debug("Port %d status: 0x%x\n", i, tmp); - if ((tmp & 0xf) == 0x03) + debug("SATA port %d status: 0x%x\n", i, tmp); + if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY) probe_ent->link_port_map |= (0x01 << i); } @@ -328,9 +378,12 @@ static int ahci_init_one(pci_dev_t pdev) u16 vendor; int rc; - memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); - probe_ent = malloc(sizeof(struct ahci_probe_ent)); + if (!probe_ent) { + printf("%s: No memory for probe_ent\n", __func__); + return -ENOMEM; + } + memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); probe_ent->dev = pdev; @@ -419,7 +472,7 @@ static void ahci_set_feature(u8 port) memset(fis, 0, sizeof(fis)); fis[0] = 0x27; fis[1] = 1 << 7; - fis[2] = ATA_CMD_SETF; + fis[2] = ATA_CMD_SET_FEATURES; fis[3] = SETFEATURES_XFER; fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; @@ -429,7 +482,8 @@ static void ahci_set_feature(u8 port) writel(1, port_mmio + PORT_CMD_ISSUE); readl(port_mmio + PORT_CMD_ISSUE); - if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, + WAIT_MS_DATAIO, 0x1)) { printf("set feature error on port %d!\n", port); } } @@ -454,7 +508,7 @@ static int ahci_port_start(u8 port) mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); if (!mem) { free(pp); - printf("No mem for table!\n"); + printf("%s: No mem for table!\n", __func__); return -ENOMEM; } @@ -535,7 +589,8 @@ static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); - if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, + WAIT_MS_DATAIO, 0x1)) { printf("timeout exit!\n"); return -1; } @@ -555,33 +610,12 @@ static char *ata_id_strcpy(u16 *target, u16 *src, int len) return (char *)target; } - -static void dump_ataid(hd_driveid_t *ataid) -{ - debug("(49)ataid->capability = 0x%x\n", ataid->capability); - debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); - debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); - debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); - debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); - debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); - debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); - debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); - debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); - debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); - debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); - debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); - debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); - debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); - debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); -} - - /* * SCSI INQUIRY command operation. */ static int ata_scsiop_inquiry(ccb *pccb) { - u8 hdr[] = { + static const u8 hdr[] = { 0, 0, 0x5, /* claim SPC-3 version compatibility */ @@ -589,7 +623,7 @@ static int ata_scsiop_inquiry(ccb *pccb) 95 - 4, }; u8 fis[20]; - u8 *tmpid; + ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS); u8 port; /* Clean ccb data buffer */ @@ -604,28 +638,29 @@ static int ata_scsiop_inquiry(ccb *pccb) /* Construct the FIS */ fis[0] = 0x27; /* Host to device FIS. */ fis[1] = 1 << 7; /* Command FIS. */ - fis[2] = ATA_CMD_IDENT; /* Command byte. */ + fis[2] = ATA_CMD_ID_ATA; /* Command byte. */ /* Read id from sata */ port = pccb->target; - if (!(tmpid = malloc(sizeof(hd_driveid_t)))) - return -ENOMEM; - if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid, - sizeof(hd_driveid_t), 0)) { + if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid, + ATA_ID_WORDS * 2, 0)) { debug("scsi_ahci: SCSI inquiry command failure.\n"); return -EIO; } if (ataid[port]) free(ataid[port]); - ataid[port] = (hd_driveid_t *) tmpid; + ataid[port] = tmpid; + ata_swap_buf_le16(tmpid, ATA_ID_WORDS); memcpy(&pccb->pdata[8], "ATA ", 8); - ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16); - ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); + ata_id_strcpy((u16 *) &pccb->pdata[16], &tmpid[ATA_ID_PROD], 16); + ata_id_strcpy((u16 *) &pccb->pdata[32], &tmpid[ATA_ID_FW_REV], 4); - dump_ataid(ataid[port]); +#ifdef DEBUG + ata_dump_id(tmpid); +#endif return 0; } @@ -665,7 +700,7 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) fis[0] = 0x27; /* Host to device FIS. */ fis[1] = 1 << 7; /* Command FIS. */ /* Command byte (read/write). */ - fis[2] = is_write ? ATA_CMD_WR_DMA : ATA_CMD_RD_DMA; + fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; while (blocks) { u16 now_blocks; /* number of blocks per iteration */ @@ -673,17 +708,21 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks); - transfer_size = ATA_BLOCKSIZE * now_blocks; + transfer_size = ATA_SECT_SIZE * now_blocks; if (transfer_size > user_buffer_size) { printf("scsi_ahci: Error: buffer too small.\n"); return -EIO; } - /* LBA address, only support LBA28 in this driver */ + /* LBA48 SATA command but only use 32bit address range within + * that. The next smaller command range (28bit) is too small. + */ fis[4] = (lba >> 0) & 0xff; fis[5] = (lba >> 8) & 0xff; fis[6] = (lba >> 16) & 0xff; - fis[7] = ((lba >> 24) & 0xf) | 0xe0; + fis[7] = 1 << 6; /* device reg: set LBA mode */ + fis[8] = ((lba >> 24) & 0xff); + fis[3] = 0xe0; /* features */ /* Block (sector) count */ fis[12] = (now_blocks >> 0) & 0xff; @@ -697,6 +736,17 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) is_write ? "WRITE" : "READ"); return -EIO; } + + /* If this transaction is a write, do a following flush. + * Writes in u-boot are so rare, and the logic to know when is + * the last write and do a flush only there is sufficiently + * difficult. Just do a flush after every write. This incurs, + * usually, one extra flush when the rare writes do happen. + */ + if (is_write) { + if (-EIO == ata_io_flush(pccb->target)) + return -EIO; + } user_buffer += transfer_size; user_buffer_size -= transfer_size; blocks -= now_blocks; @@ -713,6 +763,7 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) static int ata_scsiop_read_capacity10(ccb *pccb) { u32 cap; + u64 cap64; u32 block_size; if (!ataid[pccb->target]) { @@ -722,18 +773,11 @@ static int ata_scsiop_read_capacity10(ccb *pccb) return -EPERM; } - cap = le32_to_cpu(ataid[pccb->target]->lba_capacity); - if (cap == 0xfffffff) { - unsigned short *cap48 = ataid[pccb->target]->lba48_capacity; - if (cap48[2] || cap48[3]) { - cap = 0xffffffff; - } else { - cap = (le16_to_cpu(cap48[1]) << 16) | - (le16_to_cpu(cap48[0])); - } - } + cap64 = ata_id_n_sectors(ataid[pccb->target]); + if (cap64 > 0x100000000ULL) + cap64 = 0xffffffff; - cap = cpu_to_be32(cap); + cap = cpu_to_be32(cap64); memcpy(pccb->pdata, &cap, sizeof(cap)); block_size = cpu_to_be32((u32)512); @@ -758,12 +802,7 @@ static int ata_scsiop_read_capacity16(ccb *pccb) return -EPERM; } - cap = le32_to_cpu(ataid[pccb->target]->lba_capacity); - if (cap == 0xfffffff) { - memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap)); - cap = le64_to_cpu(cap); - } - + cap = ata_id_n_sectors(ataid[pccb->target]); cap = cpu_to_be64(cap); memcpy(pccb->pdata, &cap, sizeof(cap)); @@ -808,14 +847,14 @@ int scsi_exec(ccb *pccb) break; default: printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); - return FALSE; + return false; } if (ret) { debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); - return FALSE; + return false; } - return TRUE; + return true; } @@ -850,9 +889,12 @@ int ahci_init(u32 base) int i, rc = 0; u32 linkmap; - memset(ataid, 0, sizeof(ataid)); - probe_ent = malloc(sizeof(struct ahci_probe_ent)); + if (!probe_ent) { + printf("%s: No memory for probe_ent\n", __func__); + return -ENOMEM; + } + memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); probe_ent->host_flags = ATA_FLAG_SATA @@ -890,6 +932,42 @@ err_out: } #endif +/* + * In the general case of generic rotating media it makes sense to have a + * flush capability. It probably even makes sense in the case of SSDs because + * one cannot always know for sure what kind of internal cache/flush mechanism + * is embodied therein. At first it was planned to invoke this after the last + * write to disk and before rebooting. In practice, knowing, a priori, which + * is the last write is difficult. Because writing to the disk in u-boot is + * very rare, this flush command will be invoked after every block write. + */ +static int ata_io_flush(u8 port) +{ + u8 fis[20]; + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + u32 cmd_fis_len = 5; /* five dwords */ + + /* Preset the FIS */ + memset(fis, 0, 20); + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_FLUSH_EXT; + + memcpy((unsigned char *)pp->cmd_tbl, fis, 20); + ahci_fill_cmd_slot(pp, cmd_fis_len); + writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); + + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, + WAIT_MS_FLUSH, 0x1)) { + debug("scsi_ahci: flush command timeout on port %d.\n", port); + return -EIO; + } + + return 0; +} + + void scsi_bus_reset(void) { /*Not implement*/