X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fblock%2Ffsl_sata.c;h=3026adec0d6109b67eefd05177bff14409c326ab;hb=a35ea8070cd1e222a7c55bc32acf2e4efe80dbbb;hp=b101bd76403176f30c3c562563aa7b9e7bb01b4d;hpb=d8fffa057c9430fd0c5104ab6ff7db4cdb03db51;p=u-boot

diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c
index b101bd7640..3026adec0d 100644
--- a/drivers/block/fsl_sata.c
+++ b/drivers/block/fsl_sata.c
@@ -50,13 +50,6 @@ static struct fsl_sata_info fsl_sata_info[] = {
 #endif
 };
 
-static inline void mdelay(unsigned long msec)
-{
-	unsigned long i;
-	for (i = 0; i < msec; i++)
-		udelay(1000);
-}
-
 static inline void sdelay(unsigned long sec)
 {
 	unsigned long i;
@@ -204,27 +197,6 @@ int init_sata(int dev)
 	/* Wait the controller offline */
 	ata_wait_register(&reg->hstatus, HSTATUS_ONOFF, 0, 1000);
 
-#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
-	/*
-	 * For P1022/1013 Rev1.0 silicon, after power on SATA host
-	 * controller is configured in legacy mode instead of the
-	 * expected enterprise mode. software needs to clear bit[28]
-	 * of HControl register to change to enterprise mode from
-	 * legacy mode.
-	 */
-	{
-		u32 svr = get_svr();
-		if (IS_SVR_REV(svr, 1, 0) &&
-		    ((SVR_SOC_VER(svr) == SVR_P1022) ||
-		     (SVR_SOC_VER(svr) == SVR_P1022_E) ||
-		     (SVR_SOC_VER(svr) == SVR_P1013) ||
-		     (SVR_SOC_VER(svr) == SVR_P1013_E))) {
-			out_le32(&reg->hstatus, 0x20000000);
-			out_le32(&reg->hcontrol, 0x00000100);
-		}
-	}
-#endif
-
 	/* Set the command header base address to CHBA register to tell DMA */
 	out_le32(&reg->chba, (u32)cmd_hdr & ~0x3);