X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fclk%2Fclk_stm32f.c;h=cbcfe3a89dd780ae4bff1defde0af0d2de9f9aa4;hb=b1360e2fc9b45650e1744138702dc6938962d608;hp=a11d6dc242ba5175559834af65855bbdae8523ad;hpb=e8fb9ed2542ab6ca1946bec34a5232bde785f141;p=u-boot diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index a11d6dc242..cbcfe3a89d 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -1,8 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved * Author(s): Vikas Manocha, for STMicroelectronics. - * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -134,8 +133,12 @@ struct stm32_clk { struct stm32_pwr_regs *pwr_regs; struct stm32_clk_info info; unsigned long hse_rate; + bool pllsaip; }; +#ifdef CONFIG_VIDEO_STM32 +static const u8 plldivr_table[] = { 0, 0, 2, 3, 4, 5, 6, 7 }; +#endif static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 }; static int configure_clocks(struct udevice *dev) @@ -177,8 +180,12 @@ static int configure_clocks(struct udevice *dev) /* configure SDMMC clock */ if (priv->info.v2) { /*stm32f7 case */ - /* select PLLQ as 48MHz clock source */ - clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); + if (priv->pllsaip) + /* select PLLSAIP as 48MHz clock source */ + setbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); + else + /* select PLLQ as 48MHz clock source */ + clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); /* select 48MHz as SDMMC1 clock source */ clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL); @@ -186,17 +193,23 @@ static int configure_clocks(struct udevice *dev) /* select 48MHz as SDMMC2 clock source */ clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL); } else { /* stm32f4 case */ - /* select PLLQ as 48MHz clock source */ - clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL); + if (priv->pllsaip) + /* select PLLSAIP as 48MHz clock source */ + setbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL); + else + /* select PLLQ as 48MHz clock source */ + clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL); /* select 48MHz as SDMMC1 clock source */ clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL); } -#ifdef CONFIG_VIDEO_STM32 /* - * Configure the SAI PLL to generate LTDC pixel clock + * Configure the SAI PLL to generate LTDC pixel clock and + * 48 Mhz for SDMMC and USB */ + clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIP_MASK, + RCC_PLLSAICFGR_PLLSAIP_4); clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK, RCC_PLLSAICFGR_PLLSAIR_3); clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIN_MASK, @@ -204,18 +217,16 @@ static int configure_clocks(struct udevice *dev) clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK, RCC_DCKCFGR_PLLSAIDIVR_2 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT); -#endif + /* Enable the main PLL */ setbits_le32(®s->cr, RCC_CR_PLLON); while (!(readl(®s->cr) & RCC_CR_PLLRDY)) ; -#ifdef CONFIG_VIDEO_STM32 -/* Enable the SAI PLL */ + /* Enable the SAI PLL */ setbits_le32(®s->cr, RCC_CR_PLLSAION); while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY)) ; -#endif setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN); if (priv->info.has_overdrive) { @@ -429,7 +440,7 @@ static ulong stm32_clk_get_rate(struct clk *clk) return (sysclk >> stm32_get_apb_shift(regs, APB1)); /* APB2 CLOCK */ - case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC): + case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(DSI): switch (clk->id) { /* * particular case for SDMMC1 and SDMMC2 : @@ -484,7 +495,104 @@ static ulong stm32_clk_get_rate(struct clk *clk) static ulong stm32_set_rate(struct clk *clk, ulong rate) { +#ifdef CONFIG_VIDEO_STM32 + struct stm32_clk *priv = dev_get_priv(clk->dev); + struct stm32_rcc_regs *regs = priv->base; + u32 pllsair_rate, pllsai_vco_rate, current_rate; + u32 best_div, best_diff, diff; + u16 div; + u8 best_plldivr, best_pllsaidivr; + u8 i, j; + bool found = false; + + /* Only set_rate for LTDC clock is implemented */ + if (clk->id != STM32F7_APB2_CLOCK(LTDC)) { + pr_err("set_rate not implemented for clock index %ld\n", + clk->id); + return 0; + } + + if (rate == stm32_clk_get_rate(clk)) + /* already set to requested rate */ + return rate; + + /* get the current PLLSAIR output freq */ + pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR); + best_div = pllsair_rate / rate; + + /* look into pllsaidivr_table if this divider is available*/ + for (i = 0 ; i < sizeof(pllsaidivr_table); i++) + if (best_div == pllsaidivr_table[i]) { + /* set pll_saidivr with found value */ + clrsetbits_le32(®s->dckcfgr, + RCC_DCKCFGR_PLLSAIDIVR_MASK, + pllsaidivr_table[i]); + return rate; + } + + /* + * As no pllsaidivr value is suitable to obtain requested freq, + * test all combination of pllsaidivr * pllsair and find the one + * which give freq closest to requested rate. + */ + + pllsai_vco_rate = stm32_clk_get_pllsai_vco_rate(priv); + best_diff = ULONG_MAX; + best_pllsaidivr = 0; + best_plldivr = 0; + /* + * start at index 2 of plldivr_table as divider value at index 0 + * and 1 are 0) + */ + for (i = 2; i < sizeof(plldivr_table); i++) { + for (j = 0; j < sizeof(pllsaidivr_table); j++) { + div = plldivr_table[i] * pllsaidivr_table[j]; + current_rate = pllsai_vco_rate / div; + /* perfect combination is found ? */ + if (current_rate == rate) { + best_pllsaidivr = j; + best_plldivr = i; + found = true; + break; + } + + diff = (current_rate > rate) ? + current_rate - rate : rate - current_rate; + + /* found a better combination ? */ + if (diff < best_diff) { + best_diff = diff; + best_pllsaidivr = j; + best_plldivr = i; + } + } + + if (found) + break; + } + + /* Disable the SAI PLL */ + clrbits_le32(®s->cr, RCC_CR_PLLSAION); + + /* set pll_saidivr with found value */ + clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK, + best_pllsaidivr << RCC_DCKCFGR_PLLSAIDIVR_SHIFT); + + /* set pllsair with found value */ + clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK, + plldivr_table[best_plldivr] + << RCC_PLLSAICFGR_PLLSAIR_SHIFT); + + /* Enable the SAI PLL */ + setbits_le32(®s->cr, RCC_CR_PLLSAION); + while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY)) + ; + + div = plldivr_table[best_plldivr] * pllsaidivr_table[best_pllsaidivr]; + return pllsai_vco_rate / div; +#else return 0; +#endif } static int stm32_clk_enable(struct clk *clk) @@ -518,12 +626,17 @@ static int stm32_clk_probe(struct udevice *dev) return -EINVAL; priv->base = (struct stm32_rcc_regs *)addr; + priv->pllsaip = true; switch (dev_get_driver_data(dev)) { - case STM32F4: + case STM32F42X: + priv->pllsaip = false; + /* fallback into STM32F469 case */ + case STM32F469: memcpy(&priv->info, &stm32f4_clk_info, sizeof(struct stm32_clk_info)); break; + case STM32F7: memcpy(&priv->info, &stm32f7_clk_info, sizeof(struct stm32_clk_info));