X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fclk%2Fclk_stm32f7.c;h=f1a9e9ca44ee4341c3926e00b17cbafdd5ef5eb3;hb=033b61198997c54c4cc962ed17a755029de7ad56;hp=68d6ba0461d7bfbd8d06c88e95112e05ad4f2246;hpb=958046fc78f95a3d28b06980a7eb3ed80123c533;p=u-boot

diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c
index 68d6ba0461..f1a9e9ca44 100644
--- a/drivers/clk/clk_stm32f7.c
+++ b/drivers/clk/clk_stm32f7.c
@@ -1,9 +1,10 @@
 /*
- * (C) Copyright 2017
- * Vikas Manocha, <vikas.manocha@st.com>
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
+
 #include <common.h>
 #include <clk-uclass.h>
 #include <dm.h>
@@ -135,13 +136,15 @@ static int configure_clocks(struct udevice *dev)
 		| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
 
 	/* Configure the main PLL */
-	uint32_t pllcfgr = 0;
-	pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */
-	pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT;
-	pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;
-	pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;
-	pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;
-	writel(pllcfgr, &regs->pllcfgr);
+	setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
+	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
+			sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT);
+	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
+			sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT);
+	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
+			((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
+	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
+			sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
 
 	/* Enable the main PLL */
 	setbits_le32(&regs->cr, RCC_CR_PLLON);
@@ -224,7 +227,7 @@ static unsigned long stm32_clk_get_rate(struct clk *clk)
 		return sysclk >>= shift;
 		break;
 	default:
-		error("clock index %ld out of range\n", clk->id);
+		pr_err("clock index %ld out of range\n", clk->id);
 		return -EINVAL;
 		break;
 	}