X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fclk%2Fclk_stm32h7.c;h=f84a4d2b2f6d2d9289f34239ce72aceaf2cccc63;hb=6c1bf6c442612135bbabe0112060c8bae86fdfbc;hp=757882219a25145da6111e244d6aead53e1f03f9;hpb=1b4ce69dc2f92af719ae60891559102048c38c84;p=u-boot

diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c
index 757882219a..f84a4d2b2f 100644
--- a/drivers/clk/clk_stm32h7.c
+++ b/drivers/clk/clk_stm32h7.c
@@ -109,7 +109,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define		QSPISRC_PER_CK		3
 
 #define PWR_CR3				0x0c
-#define PWR_CR3_SDEN			BIT(2)
+#define PWR_CR3_SCUEN			BIT(2)
 #define PWR_D3CR			0x18
 #define PWR_D3CR_VOS_MASK		GENMASK(15, 14)
 #define PWR_D3CR_VOS_SHIFT		14
@@ -361,11 +361,11 @@ int configure_clocks(struct udevice *dev)
 	writel(0x0, &regs->d2ccip1r);
 	writel(0x0, &regs->d2ccip2r);
 
-	/* Set voltage scaling at scale 1 */
+	/* Set voltage scaling at scale 1 (1,15 - 1,26 Volts) */
 	clrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK,
 			VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT);
-	/* disable step down converter */
-	clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SDEN);
+	/* Lock supply configuration update */
+	clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SCUEN);
 	while (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY))
 		;