X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fddr%2Ffsl%2Finteractive.c;h=c99bd2fb6d014ffa306a42fc6f8c8c179a61bb18;hb=ab21ecef7a38dd211fe6db35c6e60800445eb6a2;hp=32ba6d820b6c207578de19a6ca157469169e6c3a;hpb=bb5783224b9b12eecf406761f82e3de2a2ca9dae;p=u-boot

diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index 32ba6d820b..c99bd2fb6d 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -154,7 +154,9 @@ static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 	static const struct options_string options[] = {
 		COMMON_TIMING(tckmin_x_ps),
 		COMMON_TIMING(tckmax_ps),
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 		COMMON_TIMING(taamin_ps),
+#endif
 		COMMON_TIMING(trcd_ps),
 		COMMON_TIMING(trp_ps),
 		COMMON_TIMING(tras_ps),
@@ -205,6 +207,8 @@ static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 
 #define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
 	sizeof((dimm_params_t *)0)->x, 0}
+#define DIMM_PARM_HEX(x) {#x, offsetof(dimm_params_t, x), \
+	sizeof((dimm_params_t *)0)->x, 1}
 
 static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 				   unsigned int ctrl_num,
@@ -220,6 +224,7 @@ static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 		DIMM_PARM(primary_sdram_width),
 		DIMM_PARM(ec_sdram_width),
 		DIMM_PARM(registered_dimm),
+		DIMM_PARM(mirrored_dimm),
 		DIMM_PARM(device_width),
 
 		DIMM_PARM(n_row_addr),
@@ -274,7 +279,27 @@ static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 		DIMM_PARM(tdqsq_max_ps),
 		DIMM_PARM(tqhs_ps),
 #endif
-
+#ifdef CONFIG_SYS_FSL_DDR4
+		DIMM_PARM_HEX(dq_mapping[0]),
+		DIMM_PARM_HEX(dq_mapping[1]),
+		DIMM_PARM_HEX(dq_mapping[2]),
+		DIMM_PARM_HEX(dq_mapping[3]),
+		DIMM_PARM_HEX(dq_mapping[4]),
+		DIMM_PARM_HEX(dq_mapping[5]),
+		DIMM_PARM_HEX(dq_mapping[6]),
+		DIMM_PARM_HEX(dq_mapping[7]),
+		DIMM_PARM_HEX(dq_mapping[8]),
+		DIMM_PARM_HEX(dq_mapping[9]),
+		DIMM_PARM_HEX(dq_mapping[10]),
+		DIMM_PARM_HEX(dq_mapping[11]),
+		DIMM_PARM_HEX(dq_mapping[12]),
+		DIMM_PARM_HEX(dq_mapping[13]),
+		DIMM_PARM_HEX(dq_mapping[14]),
+		DIMM_PARM_HEX(dq_mapping[15]),
+		DIMM_PARM_HEX(dq_mapping[16]),
+		DIMM_PARM_HEX(dq_mapping[17]),
+		DIMM_PARM(dq_mapping_ors),
+#endif
 		DIMM_PARM(rank_density),
 		DIMM_PARM(capacity),
 		DIMM_PARM(base_address),
@@ -296,6 +321,7 @@ static void print_dimm_parameters(const dimm_params_t *pdimm)
 		DIMM_PARM(primary_sdram_width),
 		DIMM_PARM(ec_sdram_width),
 		DIMM_PARM(registered_dimm),
+		DIMM_PARM(mirrored_dimm),
 		DIMM_PARM(device_width),
 
 		DIMM_PARM(n_row_addr),
@@ -314,6 +340,7 @@ static void print_dimm_parameters(const dimm_params_t *pdimm)
 		DIMM_PARM(tckmax_ps),
 
 		DIMM_PARM(caslat_x),
+		DIMM_PARM_HEX(caslat_x),
 		DIMM_PARM(taa_ps),
 		DIMM_PARM(caslat_x_minus_1),
 		DIMM_PARM(caslat_x_minus_2),
@@ -322,6 +349,9 @@ static void print_dimm_parameters(const dimm_params_t *pdimm)
 		DIMM_PARM(trcd_ps),
 		DIMM_PARM(trp_ps),
 		DIMM_PARM(tras_ps),
+#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
+		DIMM_PARM(tfaw_ps),
+#endif
 #ifdef CONFIG_SYS_FSL_DDR4
 		DIMM_PARM(trfc1_ps),
 		DIMM_PARM(trfc2_ps),
@@ -346,6 +376,27 @@ static void print_dimm_parameters(const dimm_params_t *pdimm)
 		DIMM_PARM(tdh_ps),
 		DIMM_PARM(tdqsq_max_ps),
 		DIMM_PARM(tqhs_ps),
+#endif
+#ifdef CONFIG_SYS_FSL_DDR4
+		DIMM_PARM_HEX(dq_mapping[0]),
+		DIMM_PARM_HEX(dq_mapping[1]),
+		DIMM_PARM_HEX(dq_mapping[2]),
+		DIMM_PARM_HEX(dq_mapping[3]),
+		DIMM_PARM_HEX(dq_mapping[4]),
+		DIMM_PARM_HEX(dq_mapping[5]),
+		DIMM_PARM_HEX(dq_mapping[6]),
+		DIMM_PARM_HEX(dq_mapping[7]),
+		DIMM_PARM_HEX(dq_mapping[8]),
+		DIMM_PARM_HEX(dq_mapping[9]),
+		DIMM_PARM_HEX(dq_mapping[10]),
+		DIMM_PARM_HEX(dq_mapping[11]),
+		DIMM_PARM_HEX(dq_mapping[12]),
+		DIMM_PARM_HEX(dq_mapping[13]),
+		DIMM_PARM_HEX(dq_mapping[14]),
+		DIMM_PARM_HEX(dq_mapping[15]),
+		DIMM_PARM_HEX(dq_mapping[16]),
+		DIMM_PARM_HEX(dq_mapping[17]),
+		DIMM_PARM(dq_mapping_ors),
 #endif
 	};
 	static const unsigned int n_opts = ARRAY_SIZE(options);
@@ -373,7 +424,9 @@ static void print_lowest_common_dimm_parameters(
 		const common_timing_params_t *plcd_dimm_params)
 {
 	static const struct options_string options[] = {
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 		COMMON_TIMING(taamin_ps),
+#endif
 		COMMON_TIMING(trcd_ps),
 		COMMON_TIMING(trp_ps),
 		COMMON_TIMING(tras_ps),
@@ -463,7 +516,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
 		CTRL_OPTIONS_CS(3, odt_rd_cfg),
 		CTRL_OPTIONS_CS(3, odt_wr_cfg),
 #endif
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 		CTRL_OPTIONS_CS(0, odt_rtt_norm),
 		CTRL_OPTIONS_CS(0, odt_rtt_wr),
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
@@ -621,7 +674,7 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 
 	print_option_table(options, n_opts, ddr);
 
-	for (i = 0; i < 32; i++)
+	for (i = 0; i < 64; i++)
 		printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
 }
 
@@ -714,7 +767,7 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
 	debug("fsl_ddr_regs_edit: ctrl_num = %u, "
 		"regname = %s, value = %s\n",
 		ctrl_num, regname, value_str);
-	if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
+	if (ctrl_num > CONFIG_SYS_NUM_DDR_CTLRS)
 		return;
 
 	ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
@@ -722,7 +775,7 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
 	if (handle_option_table(options, n_opts, ddr, regname, value_str))
 		return;
 
-	for (i = 0; i < 32; i++) {
+	for (i = 0; i < 64; i++) {
 		unsigned int value = simple_strtoul(value_str, NULL, 0);
 		sprintf(buf, "debug_%u", i + 1);
 		if (strcmp(buf, regname) == 0) {
@@ -753,7 +806,7 @@ static void print_memctl_options(const memctl_options_t *popts)
 		CTRL_OPTIONS_CS(3, odt_rd_cfg),
 		CTRL_OPTIONS_CS(3, odt_wr_cfg),
 #endif
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 		CTRL_OPTIONS_CS(0, odt_rtt_norm),
 		CTRL_OPTIONS_CS(0, odt_rtt_wr),
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
@@ -795,6 +848,7 @@ static void print_memctl_options(const memctl_options_t *popts)
 		CTRL_OPTIONS(twot_en),
 		CTRL_OPTIONS(threet_en),
 		CTRL_OPTIONS(registered_dimm_en),
+		CTRL_OPTIONS(mirrored_dimm),
 		CTRL_OPTIONS(ap_en),
 		CTRL_OPTIONS(x4_en),
 		CTRL_OPTIONS(bstopre),
@@ -1635,7 +1689,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
 
 	/* STEP 1:  DIMM SPD data */
 	if (do_mask & STEP_GET_SPD) {
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
 			if (!(ctrl_mask & (1 << i)))
 				continue;
 
@@ -1656,7 +1710,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
 
 	/* STEP 2:  DIMM Parameters */
 	if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
 			if (!(ctrl_mask & (1 << i)))
 				continue;
 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
@@ -1675,7 +1729,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
 
 	/* STEP 3:  Common Parameters */
 	if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
 			if (!(ctrl_mask & (1 << i)))
 				continue;
 			printf("\"lowest common\" DIMM parameters:  "
@@ -1689,7 +1743,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
 
 	/* STEP 4:  User Configuration Options */
 	if (do_mask & STEP_GATHER_OPTS) {
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
 			if (!(ctrl_mask & (1 << i)))
 				continue;
 			printf("User Config Options: Controller=%u\n", i);
@@ -1701,7 +1755,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
 
 	/* STEP 5:  Address assignment */
 	if (do_mask & STEP_ASSIGN_ADDRESSES) {
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
 			if (!(ctrl_mask & (1 << i)))
 				continue;
 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
@@ -1716,7 +1770,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
 
 	/* STEP 6:  computed controller register values */
 	if (do_mask & STEP_COMPUTE_REGS) {
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
 			if (!(ctrl_mask & (1 << i)))
 				continue;
 			printf("Computed Register Values: Controller=%u\n", i);
@@ -1807,7 +1861,7 @@ int fsl_ddr_interactive_env_var_exists(void)
 {
 	char buffer[CONFIG_SYS_CBSIZE];
 
-	if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
+	if (env_get_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
 		return 1;
 
 	return 0;
@@ -1837,11 +1891,11 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
 	};
 
 	if (var_is_set) {
-		if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) {
+		if (env_get_f("ddr_interactive", buffer2,
+			      CONFIG_SYS_CBSIZE) > 0)
 			p = buffer2;
-		} else {
+		else
 			var_is_set = 0;
-		}
 	}
 
 	/*