X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Ffpga%2FACEX1K.c;h=1627f0e6ffdeb7169e6ce20920f2e10105f2315b;hb=40d500212f74c92ef014ae8df697416e160ee743;hp=3f7967782bb3ff0b5e7fac59d40793b2d68d4cfe;hpb=c645b181a9a848996d54a5e358bedabae1da566a;p=u-boot diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index 3f7967782b..1627f0e6ff 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -5,27 +5,11 @@ * (C) Copyright 2002 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * + * SPDX-License-Identifier: GPL-2.0+ */ #include /* core U-Boot definitions */ +#include #include /* ACEX device family */ /* Define FPGA_DEBUG to get debug printf's */ @@ -48,14 +32,13 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ #endif -static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize ); -static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); -/* static int ACEX1K_ps_info( Altera_desc *desc ); */ -static int ACEX1K_ps_reloc( Altera_desc *desc, ulong reloc_offset ); +static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize); +static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize); +/* static int ACEX1K_ps_info(Altera_desc *desc); */ /* ------------------------------------------------------------------------- */ /* ACEX1K Generic Implementation */ -int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize) +int ACEX1K_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -75,7 +58,7 @@ int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize) return ret_val; } -int ACEX1K_dump (Altera_desc * desc, void *buf, size_t bsize) +int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -101,35 +84,10 @@ int ACEX1K_info( Altera_desc *desc ) } -int ACEX1K_reloc (Altera_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume a failure */ - - if (desc->family != Altera_ACEX1K) { - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - return FPGA_FAIL; - } else - switch (desc->iface) { - case passive_serial: - ret_val = ACEX1K_ps_reloc (desc, reloc_offset); - break; - - /* Add new interface types here */ - - default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); - } - - return ret_val; -} - - /* ------------------------------------------------------------------------- */ /* ACEX1K Passive Serial Generic Implementation */ -static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize) +static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns; @@ -166,7 +124,7 @@ static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize) } /* Establish the initial state */ - (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */ + (*fn->config) (true, true, cookie); /* Assert nCONFIG */ udelay(2); /* T_cfg > 2us */ @@ -178,7 +136,7 @@ static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize) return FPGA_FAIL; } - (*fn->config) (FALSE, TRUE, cookie); /* Deassert nCONFIG */ + (*fn->config) (false, true, cookie); /* Deassert nCONFIG */ udelay(2); /* T_cf2st1 < 4us */ /* Wait for nSTATUS to be released (i.e. deasserted) */ @@ -218,13 +176,13 @@ static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize) i = 8; do { /* Deassert the clock */ - (*fn->clk) (FALSE, TRUE, cookie); + (*fn->clk) (false, true, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->data) ( (val & 0x01), TRUE, cookie); + (*fn->data) ((val & 0x01), true, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->clk) (true, true, cookie); CONFIG_FPGA_DELAY (); val >>= 1; i --; @@ -258,9 +216,9 @@ static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize) for (i = 0; i < 12; i++) { CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ } ret_val = FPGA_SUCCESS; @@ -282,7 +240,7 @@ static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize) return ret_val; } -static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize) +static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ @@ -290,73 +248,3 @@ static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } - -static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume the worst */ - Altera_ACEX1K_Passive_Serial_fns *fn_r, *fn = - (Altera_ACEX1K_Passive_Serial_fns *) (desc->iface_fns); - - if (fn) { - ulong addr; - - /* Get the relocated table address */ - addr = (ulong) fn + reloc_offset; - fn_r = (Altera_ACEX1K_Passive_Serial_fns *) addr; - - if (!fn_r->relocated) { - - if (memcmp (fn_r, fn, - sizeof (Altera_ACEX1K_Passive_Serial_fns)) - == 0) { - /* good copy of the table, fix the descriptor pointer */ - desc->iface_fns = fn_r; - } else { - PRINTF ("%s: Invalid function table at 0x%p\n", - __FUNCTION__, fn_r); - return FPGA_FAIL; - } - - PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, - desc); - - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Altera_pre_fn) addr; - - addr = (ulong) (fn->config) + reloc_offset; - fn_r->config = (Altera_config_fn) addr; - - addr = (ulong) (fn->status) + reloc_offset; - fn_r->status = (Altera_status_fn) addr; - - addr = (ulong) (fn->done) + reloc_offset; - fn_r->done = (Altera_done_fn) addr; - - addr = (ulong) (fn->clk) + reloc_offset; - fn_r->clk = (Altera_clk_fn) addr; - - addr = (ulong) (fn->data) + reloc_offset; - fn_r->data = (Altera_data_fn) addr; - - addr = (ulong) (fn->abort) + reloc_offset; - fn_r->abort = (Altera_abort_fn) addr; - - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Altera_post_fn) addr; - - fn_r->relocated = TRUE; - - } else { - /* this table has already been moved */ - /* XXX - should check to see if the descriptor is correct */ - desc->iface_fns = fn_r; - } - - ret_val = FPGA_SUCCESS; - } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); - } - - return ret_val; - -}