X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Ffpga%2Fvirtex2.c;h=02773d6a0e4841306f793bfb9c8322384d618357;hb=f3f2af3bdf2af89d0621aa0fbd94a918e4447081;hp=d1b4d15b711cf6f904a371389daf541d9167e003;hpb=cd77dd109c4a439519a78c32eddc42bdebc7a61f;p=u-boot

diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index d1b4d15b71..02773d6a0e 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -1,26 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2002
  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  * Keith Outwater, keith_outwater@mvis.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
  */
 
 /*
@@ -29,6 +11,7 @@
  */
 
 #include <common.h>
+#include <console.h>
 #include <virtex2.h>
 
 #if 0
@@ -101,25 +84,26 @@
 #define CONFIG_SYS_FPGA_WAIT_CONFIG	CONFIG_SYS_HZ/5	/* 200 ms */
 #endif
 
-static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize);
-static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize);
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
 
-static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize);
-static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize);
+static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
 
-int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
+			bitstream_type bstype)
 {
 	int ret_val = FPGA_FAIL;
 
 	switch (desc->iface) {
 	case slave_serial:
 		PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
-		ret_val = Virtex2_ss_load (desc, buf, bsize);
+		ret_val = virtex2_ss_load(desc, buf, bsize);
 		break;
 
 	case slave_selectmap:
 		PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
-		ret_val = Virtex2_ssm_load (desc, buf, bsize);
+		ret_val = virtex2_ssm_load(desc, buf, bsize);
 		break;
 
 	default:
@@ -129,19 +113,19 @@ int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize)
 	return ret_val;
 }
 
-int Virtex2_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 
 	switch (desc->iface) {
 	case slave_serial:
 		PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
-		ret_val = Virtex2_ss_dump (desc, buf, bsize);
+		ret_val = virtex2_ss_dump(desc, buf, bsize);
 		break;
 
 	case slave_parallel:
 		PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
-		ret_val = Virtex2_ssm_dump (desc, buf, bsize);
+		ret_val = virtex2_ssm_dump(desc, buf, bsize);
 		break;
 
 	default:
@@ -151,7 +135,7 @@ int Virtex2_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 	return ret_val;
 }
 
-int Virtex2_info (Xilinx_desc * desc)
+static int virtex2_info(xilinx_desc *desc)
 {
 	return FPGA_SUCCESS;
 }
@@ -170,10 +154,10 @@ int Virtex2_info (Xilinx_desc * desc)
  *    INIT_B and DONE lines.  If both are high, configuration has
  *    succeeded. Congratulations!
  */
-static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
-	Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
+	xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
 
 	PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
 			__FUNCTION__, __LINE__, fn);
@@ -221,7 +205,7 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
 		 * There is no maximum value for the pulse width.  Check to make
 		 * sure that INIT_B goes low after assertion of PROG_B
 		 */
-		(*fn->pgm) (TRUE, TRUE, cookie);
+		(*fn->pgm) (true, true, cookie);
 		udelay (10);
 		ts = get_timer (0);
 		do {
@@ -234,9 +218,9 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
 			}
 		} while (!(*fn->init) (cookie));
 
-		(*fn->pgm) (FALSE, TRUE, cookie);
+		(*fn->pgm) (false, true, cookie);
 		CONFIG_FPGA_DELAY ();
-		(*fn->clk) (TRUE, TRUE, cookie);
+		(*fn->clk) (true, true, cookie);
 
 		/*
 		 * Start a timer and wait for INIT_B to go high
@@ -253,8 +237,8 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
 			}
 		} while ((*fn->init) (cookie) && (*fn->busy) (cookie));
 
-		(*fn->wr) (TRUE, TRUE, cookie);
-		(*fn->cs) (TRUE, TRUE, cookie);
+		(*fn->wr) (true, true, cookie);
+		(*fn->cs) (true, true, cookie);
 
 		udelay (10000);
 
@@ -286,15 +270,15 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
 			}
 #endif
 
-			(*fn->wdata) (data[bytecount++], TRUE, cookie);
+			(*fn->wdata) (data[bytecount++], true, cookie);
 			CONFIG_FPGA_DELAY ();
 
 			/*
 			 * Cycle the clock pin
 			 */
-			(*fn->clk) (FALSE, TRUE, cookie);
+			(*fn->clk) (false, true, cookie);
 			CONFIG_FPGA_DELAY ();
-			(*fn->clk) (TRUE, TRUE, cookie);
+			(*fn->clk) (true, true, cookie);
 
 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
 			ts = get_timer (0);
@@ -319,8 +303,8 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
 		 * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
 		 */
 		CONFIG_FPGA_DELAY ();
-		(*fn->cs) (FALSE, TRUE, cookie);
-		(*fn->wr) (FALSE, TRUE, cookie);
+		(*fn->cs) (false, true, cookie);
+		(*fn->wr) (false, true, cookie);
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 		putc ('\n');
@@ -369,10 +353,10 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
 /*
  * Read the FPGA configuration data
  */
-static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
-	Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
+	xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
 
 	if (fn) {
 		unsigned char *data = (unsigned char *) buf;
@@ -381,8 +365,8 @@ static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 
 		printf ("Starting Dump of FPGA Device %d...\n", cookie);
 
-		(*fn->cs) (TRUE, TRUE, cookie);
-		(*fn->clk) (TRUE, TRUE, cookie);
+		(*fn->cs) (true, true, cookie);
+		(*fn->clk) (true, true, cookie);
 
 		while (bytecount < bsize) {
 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
@@ -394,8 +378,8 @@ static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 			/*
 			 * Cycle the clock and read the data
 			 */
-			(*fn->clk) (FALSE, TRUE, cookie);
-			(*fn->clk) (TRUE, TRUE, cookie);
+			(*fn->clk) (false, true, cookie);
+			(*fn->clk) (true, true, cookie);
 			(*fn->rdata) (&(data[bytecount++]), cookie);
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
@@ -406,9 +390,9 @@ static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 		/*
 		 * Deassert CS_B and cycle the clock to deselect the device.
 		 */
-		(*fn->cs) (FALSE, FALSE, cookie);
-		(*fn->clk) (FALSE, TRUE, cookie);
-		(*fn->clk) (TRUE, TRUE, cookie);
+		(*fn->cs) (false, false, cookie);
+		(*fn->clk) (false, true, cookie);
+		(*fn->clk) (true, true, cookie);
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 		putc ('\n');
@@ -421,16 +405,22 @@ static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 	return ret_val;
 }
 
-static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
 	return FPGA_FAIL;
 }
 
-static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
 	return FPGA_FAIL;
 }
 
 /* vim: set ts=4 tw=78: */
+
+struct xilinx_fpga_op virtex2_op = {
+	.load = virtex2_load,
+	.dump = virtex2_dump,
+	.info = virtex2_info,
+};