X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Ffpga%2Fvirtex2.c;h=0d2d9a4693264684bbeb5167790057c0ae07b732;hb=42800ffa7997082e2466c772bc2395dff0c95e3a;hp=50d0921844fa84019f9a4a072b6f9513691698a7;hpb=be4880ebe4355e8782be4af4b337a1b98dffcbe3;p=u-boot

diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index 50d0921844..0d2d9a4693 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -3,24 +3,7 @@
  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  * Keith Outwater, keith_outwater@mvis.com
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /*
@@ -101,27 +84,26 @@
 #define CONFIG_SYS_FPGA_WAIT_CONFIG	CONFIG_SYS_HZ/5	/* 200 ms */
 #endif
 
-static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize);
-static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize);
-static int Virtex2_ssm_reloc (Xilinx_desc * desc, ulong reloc_offset);
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
 
-static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize);
-static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize);
-static int Virtex2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset);
+static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
 
-int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
+			bitstream_type bstype)
 {
 	int ret_val = FPGA_FAIL;
 
 	switch (desc->iface) {
 	case slave_serial:
 		PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
-		ret_val = Virtex2_ss_load (desc, buf, bsize);
+		ret_val = virtex2_ss_load(desc, buf, bsize);
 		break;
 
 	case slave_selectmap:
 		PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
-		ret_val = Virtex2_ssm_load (desc, buf, bsize);
+		ret_val = virtex2_ssm_load(desc, buf, bsize);
 		break;
 
 	default:
@@ -131,19 +113,19 @@ int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize)
 	return ret_val;
 }
 
-int Virtex2_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 
 	switch (desc->iface) {
 	case slave_serial:
 		PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
-		ret_val = Virtex2_ss_dump (desc, buf, bsize);
+		ret_val = virtex2_ss_dump(desc, buf, bsize);
 		break;
 
 	case slave_parallel:
 		PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
-		ret_val = Virtex2_ssm_dump (desc, buf, bsize);
+		ret_val = virtex2_ssm_dump(desc, buf, bsize);
 		break;
 
 	default:
@@ -153,36 +135,11 @@ int Virtex2_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 	return ret_val;
 }
 
-int Virtex2_info (Xilinx_desc * desc)
+static int virtex2_info(xilinx_desc *desc)
 {
 	return FPGA_SUCCESS;
 }
 
-int Virtex2_reloc (Xilinx_desc * desc, ulong reloc_offset)
-{
-	int ret_val = FPGA_FAIL;
-
-	if (desc->family != Xilinx_Virtex2) {
-		printf ("%s: Unsupported family type, %d\n",
-				__FUNCTION__, desc->family);
-		return FPGA_FAIL;
-	} else
-		switch (desc->iface) {
-		case slave_serial:
-			ret_val = Virtex2_ss_reloc (desc, reloc_offset);
-			break;
-
-		case slave_selectmap:
-			ret_val = Virtex2_ssm_reloc (desc, reloc_offset);
-			break;
-
-		default:
-			printf ("%s: Unsupported interface type, %d\n",
-					__FUNCTION__, desc->iface);
-		}
-	return ret_val;
-}
-
 /*
  * Virtex-II Slave SelectMap configuration loader. Configuration via
  * SelectMap is as follows:
@@ -197,10 +154,10 @@ int Virtex2_reloc (Xilinx_desc * desc, ulong reloc_offset)
  *    INIT_B and DONE lines.  If both are high, configuration has
  *    succeeded. Congratulations!
  */
-static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
-	Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
+	xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
 
 	PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
 			__FUNCTION__, __LINE__, fn);
@@ -248,7 +205,7 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
 		 * There is no maximum value for the pulse width.  Check to make
 		 * sure that INIT_B goes low after assertion of PROG_B
 		 */
-		(*fn->pgm) (TRUE, TRUE, cookie);
+		(*fn->pgm) (true, true, cookie);
 		udelay (10);
 		ts = get_timer (0);
 		do {
@@ -261,9 +218,9 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
 			}
 		} while (!(*fn->init) (cookie));
 
-		(*fn->pgm) (FALSE, TRUE, cookie);
+		(*fn->pgm) (false, true, cookie);
 		CONFIG_FPGA_DELAY ();
-		(*fn->clk) (TRUE, TRUE, cookie);
+		(*fn->clk) (true, true, cookie);
 
 		/*
 		 * Start a timer and wait for INIT_B to go high
@@ -280,8 +237,8 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
 			}
 		} while ((*fn->init) (cookie) && (*fn->busy) (cookie));
 
-		(*fn->wr) (TRUE, TRUE, cookie);
-		(*fn->cs) (TRUE, TRUE, cookie);
+		(*fn->wr) (true, true, cookie);
+		(*fn->cs) (true, true, cookie);
 
 		udelay (10000);
 
@@ -313,15 +270,15 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
 			}
 #endif
 
-			(*fn->wdata) (data[bytecount++], TRUE, cookie);
+			(*fn->wdata) (data[bytecount++], true, cookie);
 			CONFIG_FPGA_DELAY ();
 
 			/*
 			 * Cycle the clock pin
 			 */
-			(*fn->clk) (FALSE, TRUE, cookie);
+			(*fn->clk) (false, true, cookie);
 			CONFIG_FPGA_DELAY ();
-			(*fn->clk) (TRUE, TRUE, cookie);
+			(*fn->clk) (true, true, cookie);
 
 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
 			ts = get_timer (0);
@@ -346,8 +303,8 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
 		 * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
 		 */
 		CONFIG_FPGA_DELAY ();
-		(*fn->cs) (FALSE, TRUE, cookie);
-		(*fn->wr) (FALSE, TRUE, cookie);
+		(*fn->cs) (false, true, cookie);
+		(*fn->wr) (false, true, cookie);
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 		putc ('\n');
@@ -396,10 +353,10 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
 /*
  * Read the FPGA configuration data
  */
-static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
-	Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
+	xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
 
 	if (fn) {
 		unsigned char *data = (unsigned char *) buf;
@@ -408,8 +365,8 @@ static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 
 		printf ("Starting Dump of FPGA Device %d...\n", cookie);
 
-		(*fn->cs) (TRUE, TRUE, cookie);
-		(*fn->clk) (TRUE, TRUE, cookie);
+		(*fn->cs) (true, true, cookie);
+		(*fn->clk) (true, true, cookie);
 
 		while (bytecount < bsize) {
 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
@@ -421,8 +378,8 @@ static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 			/*
 			 * Cycle the clock and read the data
 			 */
-			(*fn->clk) (FALSE, TRUE, cookie);
-			(*fn->clk) (TRUE, TRUE, cookie);
+			(*fn->clk) (false, true, cookie);
+			(*fn->clk) (true, true, cookie);
 			(*fn->rdata) (&(data[bytecount++]), cookie);
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
@@ -433,9 +390,9 @@ static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 		/*
 		 * Deassert CS_B and cycle the clock to deselect the device.
 		 */
-		(*fn->cs) (FALSE, FALSE, cookie);
-		(*fn->clk) (FALSE, TRUE, cookie);
-		(*fn->clk) (TRUE, TRUE, cookie);
+		(*fn->cs) (false, false, cookie);
+		(*fn->clk) (false, true, cookie);
+		(*fn->clk) (true, true, cookie);
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 		putc ('\n');
@@ -448,107 +405,22 @@ static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 	return ret_val;
 }
 
-/*
- * Relocate the addresses in the function table from FLASH (or ROM,
- * or whatever) to RAM.
- */
-static int Virtex2_ssm_reloc (Xilinx_desc * desc, ulong reloc_offset)
-{
-	ulong addr;
-	int ret_val = FPGA_FAIL;
-	Xilinx_Virtex2_Slave_SelectMap_fns *fn_r, *fn =
-			(Xilinx_Virtex2_Slave_SelectMap_fns *) (desc->iface_fns);
-
-	if (fn) {
-		/*
-		 * Get the relocated table address
-		 */
-		addr = (ulong) fn + reloc_offset;
-		fn_r = (Xilinx_Virtex2_Slave_SelectMap_fns *) addr;
-
-		/*
-		 * Check to see if the table has already been relocated.  If not, do
-		 * a sanity check to make sure there is a faithful copy of the
-		 * FLASH based function table in RAM, then adjust the table.
-		 */
-		if (!fn_r->relocated) {
-			if (memcmp
-				(fn_r, fn, sizeof (Xilinx_Virtex2_Slave_SelectMap_fns))
-				== 0) {
-				desc->iface_fns = fn_r;
-			} else {
-				PRINTF ("%s:%d: Invalid function table at 0x%p\n",
-						__FUNCTION__, __LINE__, fn_r);
-				return FPGA_FAIL;
-			}
-
-			PRINTF ("%s:%d: Relocating descriptor at 0x%p\n",
-					__FUNCTION__, __LINE__, desc);
-
-			addr = (ulong) (fn->pre) + reloc_offset;
-			fn_r->pre = (Xilinx_pre_fn) addr;
-			addr = (ulong) (fn->pgm) + reloc_offset;
-			fn_r->pgm = (Xilinx_pgm_fn) addr;
-			addr = (ulong) (fn->init) + reloc_offset;
-			fn_r->init = (Xilinx_init_fn) addr;
-			addr = (ulong) (fn->done) + reloc_offset;
-			fn_r->done = (Xilinx_done_fn) addr;
-			addr = (ulong) (fn->err) + reloc_offset;
-			fn_r->err = (Xilinx_err_fn) addr;
-			addr = (ulong) (fn->clk) + reloc_offset;
-			fn_r->clk = (Xilinx_clk_fn) addr;
-			addr = (ulong) (fn->cs) + reloc_offset;
-			fn_r->cs = (Xilinx_cs_fn) addr;
-			addr = (ulong) (fn->wr) + reloc_offset;
-			fn_r->wr = (Xilinx_wr_fn) addr;
-			addr = (ulong) (fn->rdata) + reloc_offset;
-			fn_r->rdata = (Xilinx_rdata_fn) addr;
-			addr = (ulong) (fn->wdata) + reloc_offset;
-			fn_r->wdata = (Xilinx_wdata_fn) addr;
-			addr = (ulong) (fn->busy) + reloc_offset;
-			fn_r->busy = (Xilinx_busy_fn) addr;
-			addr = (ulong) (fn->abort) + reloc_offset;
-			fn_r->abort = (Xilinx_abort_fn) addr;
-			addr = (ulong) (fn->post) + reloc_offset;
-			fn_r->post = (Xilinx_post_fn) addr;
-			fn_r->relocated = TRUE;
-		} else {
-			printf ("%s:%d: Function table @0x%p has already been relocated\n", __FUNCTION__, __LINE__, fn_r);
-			desc->iface_fns = fn_r;
-		}
-		ret_val = FPGA_SUCCESS;
-	} else {
-		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
-	}
-	return ret_val;
-}
-
-static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
 	return FPGA_FAIL;
 }
 
-static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
 	return FPGA_FAIL;
 }
 
-static int Virtex2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
-{
-	int ret_val = FPGA_FAIL;
-	Xilinx_Virtex2_Slave_Serial_fns *fn =
-			(Xilinx_Virtex2_Slave_Serial_fns *) (desc->iface_fns);
-
-	if (fn) {
-		printf ("%s:%d: Slave Serial Loading is unsupported\n",
-				__FUNCTION__, __LINE__);
-	} else {
-		printf ("%s:%d: NULL Interface function table!\n",
-				__FUNCTION__, __LINE__);
-	}
-	return ret_val;
-}
-
 /* vim: set ts=4 tw=78: */
+
+struct xilinx_fpga_op virtex2_op = {
+	.load = virtex2_load,
+	.dump = virtex2_dump,
+	.info = virtex2_info,
+};