X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Ffpga%2Fzynqpl.c;h=fd37d18c7f474944348b4f9c8c484f7d386ba449;hb=51b2411946e5f247f26fde41a7227a002270d376;hp=6a74f8961063c278a4088616e0a512ff75ddbeaa;hpb=746667f1e56bf08d03e66a178df3c4f4f6c806e1;p=u-boot

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 6a74f89610..fd37d18c7f 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -1,13 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2012-2013, Xilinx, Michal Simek
  *
  * (C) Copyright 2012
  * Joe Hershberger <joe.hershberger@ni.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
+#include <console.h>
 #include <asm/io.h>
 #include <fs.h>
 #include <zynqpl.h>
@@ -16,6 +16,7 @@
 #include <asm/arch/sys_proto.h>
 
 #define DEVCFG_CTRL_PCFG_PROG_B		0x40000000
+#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK	0x00001000
 #define DEVCFG_ISR_FATAL_ERROR_MASK	0x00740040
 #define DEVCFG_ISR_ERROR_FLAGS_MASK	0x00340840
 #define DEVCFG_ISR_RX_FIFO_OV		0x00040000
@@ -37,11 +38,6 @@
 #define CONFIG_SYS_FPGA_PROG_TIME	(CONFIG_SYS_HZ * 4) /* 4 s */
 #endif
 
-static int zynq_info(xilinx_desc *desc)
-{
-	return FPGA_SUCCESS;
-}
-
 #define DUMMY_WORD	0xffffffff
 
 /* Xilinx binary format header */
@@ -209,9 +205,24 @@ static int zynq_dma_xfer_init(bitstream_type bstype)
 		/* Setting PCFG_PROG_B signal to high */
 		control = readl(&devcfg_base->ctrl);
 		writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
+
+		/*
+		 * Delay is required if AES efuse is selected as
+		 * key source.
+		 */
+		if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
+			mdelay(5);
+
 		/* Setting PCFG_PROG_B signal to low */
 		writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
 
+		/*
+		 * Delay is required if AES efuse is selected as
+		 * key source.
+		 */
+		if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
+			mdelay(5);
+
 		/* Polling the PCAP_INIT status for Reset */
 		ts = get_timer(0);
 		while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
@@ -480,16 +491,9 @@ static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
 }
 #endif
 
-static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
-{
-	return FPGA_FAIL;
-}
-
 struct xilinx_fpga_op zynq_op = {
 	.load = zynq_load,
 #if defined(CONFIG_CMD_FPGA_LOADFS)
 	.loadfs = zynq_loadfs,
 #endif
-	.dump = zynq_dump,
-	.info = zynq_info,
 };