X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fi2c%2Fmxs_i2c.c;h=de3b19402b4af1c2f8a97283a77a0d92d034b0ed;hb=ad3091ad03e39f88c0bcc566c7a691c4475e2c40;hp=2a193c220d7b41252dd35b5870dfee8c07b59706;hpb=fa7a51cb8272bd6076ea4701fd6bdc65a68703ba;p=u-boot diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c index 2a193c220d..de3b19402b 100644 --- a/drivers/i2c/mxs_i2c.c +++ b/drivers/i2c/mxs_i2c.c @@ -10,24 +10,12 @@ * Which was based on a (non-working) driver which was: * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * + * SPDX-License-Identifier: GPL-2.0+ */ #include #include +#include #include #include #include @@ -36,10 +24,11 @@ #define MXS_I2C_MAX_TIMEOUT 1000000 -void mxs_i2c_reset(void) +static void mxs_i2c_reset(void) { struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; int ret; + int speed = i2c_get_bus_speed(); ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg); if (ret) { @@ -53,9 +42,11 @@ void mxs_i2c_reset(void) &i2c_regs->hw_i2c_ctrl1_clr); writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set); + + i2c_set_bus_speed(speed); } -void mxs_i2c_setup_read(uint8_t chip, int len) +static void mxs_i2c_setup_read(uint8_t chip, int len) { struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; @@ -73,16 +64,17 @@ void mxs_i2c_setup_read(uint8_t chip, int len) writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set); } -void mxs_i2c_write(uchar chip, uint addr, int alen, +static int mxs_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int blen, int stop) { struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; - uint32_t data; + uint32_t data, tmp; int i, remain, off; + int timeout = MXS_I2C_MAX_TIMEOUT; if ((alen > 4) || (alen == 0)) { debug("MXS I2C: Invalid address length\n"); - return; + return -EINVAL; } if (stop) @@ -115,9 +107,22 @@ void mxs_i2c_write(uchar chip, uint addr, int alen, writel(data >> remain, &i2c_regs->hw_i2c_data); writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set); + + while (--timeout) { + tmp = readl(&i2c_regs->hw_i2c_queuestat); + if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY) + break; + } + + if (!timeout) { + debug("MXS I2C: Failed transmitting data!\n"); + return -EINVAL; + } + + return 0; } -int mxs_i2c_wait_for_ack(void) +static int mxs_i2c_wait_for_ack(void) { struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; uint32_t tmp; @@ -159,10 +164,16 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; uint32_t tmp = 0; + int timeout = MXS_I2C_MAX_TIMEOUT; int ret; int i; - mxs_i2c_write(chip, addr, alen, NULL, 0, 0); + ret = mxs_i2c_write(chip, addr, alen, NULL, 0, 0); + if (ret) { + debug("MXS I2C: Failed writing address\n"); + return ret; + } + ret = mxs_i2c_wait_for_ack(); if (ret) { debug("MXS I2C: Failed writing address\n"); @@ -178,9 +189,17 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) for (i = 0; i < len; i++) { if (!(i & 3)) { - while (readl(&i2c_regs->hw_i2c_queuestat) & - I2C_QUEUESTAT_RD_QUEUE_EMPTY) - ; + while (--timeout) { + tmp = readl(&i2c_regs->hw_i2c_queuestat); + if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY)) + break; + } + + if (!timeout) { + debug("MXS I2C: Failed receiving data!\n"); + return -ETIMEDOUT; + } + tmp = readl(&i2c_regs->hw_i2c_queuedata); } buffer[i] = tmp & 0xff; @@ -193,7 +212,12 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) { int ret; - mxs_i2c_write(chip, addr, alen, buffer, len, 1); + ret = mxs_i2c_write(chip, addr, alen, buffer, len, 1); + if (ret) { + debug("MXS I2C: Failed writing address\n"); + return ret; + } + ret = mxs_i2c_wait_for_ack(); if (ret) debug("MXS I2C: Failed writing address\n"); @@ -204,43 +228,72 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) int i2c_probe(uchar chip) { int ret; - mxs_i2c_write(chip, 0, 1, NULL, 0, 1); - ret = mxs_i2c_wait_for_ack(); + ret = mxs_i2c_write(chip, 0, 1, NULL, 0, 1); + if (!ret) + ret = mxs_i2c_wait_for_ack(); mxs_i2c_reset(); return ret; } -void i2c_init(int speed, int slaveadd) +int i2c_set_bus_speed(unsigned int speed) { struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; + /* + * The timing derivation algorithm. There is no documentation for this + * algorithm available, it was derived by using the scope and fiddling + * with constants until the result observed on the scope was good enough + * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be + * possible to assume the algorithm works for other frequencies as well. + * + * Note it was necessary to cap the frequency on both ends as it's not + * possible to configure completely arbitrary frequency for the I2C bus + * clock. + */ + uint32_t clk = mxc_get_clock(MXC_XTAL_CLK); + uint32_t base = ((clk / speed) - 38) / 2; + uint16_t high_count = base + 3; + uint16_t low_count = base - 3; + uint16_t rcv_count = (high_count * 3) / 4; + uint16_t xmit_count = low_count / 4; + + if (speed > 540000) { + printf("MXS I2C: Speed too high (%d Hz)\n", speed); + return -EINVAL; + } - mxs_i2c_reset(); - - switch (speed) { - case 100000: - writel((0x0078 << I2C_TIMING0_HIGH_COUNT_OFFSET) | - (0x0030 << I2C_TIMING0_RCV_COUNT_OFFSET), - &i2c_regs->hw_i2c_timing0); - writel((0x0080 << I2C_TIMING1_LOW_COUNT_OFFSET) | - (0x0030 << I2C_TIMING1_XMIT_COUNT_OFFSET), - &i2c_regs->hw_i2c_timing1); - break; - case 400000: - writel((0x000f << I2C_TIMING0_HIGH_COUNT_OFFSET) | - (0x0007 << I2C_TIMING0_RCV_COUNT_OFFSET), - &i2c_regs->hw_i2c_timing0); - writel((0x001f << I2C_TIMING1_LOW_COUNT_OFFSET) | - (0x000f << I2C_TIMING1_XMIT_COUNT_OFFSET), - &i2c_regs->hw_i2c_timing1); - break; - default: - printf("MXS I2C: Invalid speed selected (%d Hz)\n", speed); - return; + if (speed < 12000) { + printf("MXS I2C: Speed too low (%d Hz)\n", speed); + return -EINVAL; } - writel((0x0015 << I2C_TIMING2_BUS_FREE_OFFSET) | - (0x000d << I2C_TIMING2_LEADIN_COUNT_OFFSET), + writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0); + writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1); + + writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) | + (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET), &i2c_regs->hw_i2c_timing2); + return 0; +} + +unsigned int i2c_get_bus_speed(void) +{ + struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; + uint32_t clk = mxc_get_clock(MXC_XTAL_CLK); + uint32_t timing0; + + timing0 = readl(&i2c_regs->hw_i2c_timing0); + /* + * This is a reverse version of the algorithm presented in + * i2c_set_bus_speed(). Please refer there for details. + */ + return clk / ((((timing0 >> 16) - 3) * 2) + 38); +} + +void i2c_init(int speed, int slaveadd) +{ + mxs_i2c_reset(); + i2c_set_bus_speed(speed); + return; }