X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fmisc%2FKconfig;h=f1c15cb9fa4060eb62a1606930eb5f6794e63509;hb=76cc372879e2f2f0467e8a3875f097d189647793;hp=c40f6b577f3bc9a862e5616ccc9fb50859724224;hpb=ec8fb48ce98987065493b27422200897cf0909f8;p=u-boot

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index c40f6b577f..f1c15cb9fa 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -20,6 +20,27 @@ config ALTERA_SYSID
 	  Select this to enable a sysid for Altera devices. Please find
 	  details on the "Embedded Peripherals IP User Guide" of Altera.
 
+config ATSHA204A
+	bool "Support for Atmel ATSHA204A module"
+	depends on MISC
+	help
+	   Enable support for I2C connected Atmel's ATSHA204A
+	   CryptoAuthentication module found for example on the Turris Omnia
+	   board.
+
+config ROCKCHIP_EFUSE
+        bool "Rockchip e-fuse support"
+	depends on MISC
+	help
+	  Enable (read-only) access for the e-fuse block found in Rockchip
+	  SoCs: accesses can either be made using byte addressing and a length
+	  or through child-nodes that are generated based on the e-fuse map
+	  retrieved from the DTS.
+
+	  This driver currently supports the RK3399 only, but can easily be
+	  extended (by porting the read function from the Linux kernel sources)
+	  to support other recent Rockchip devices.
+
 config CMD_CROS_EC
 	bool "Enable crosec command"
 	depends on CROS_EC
@@ -75,6 +96,14 @@ config CROS_EC_SPI
 	  provides a faster and more robust interface than I2C but the bugs
 	  are less interesting.
 
+config DS4510
+	bool "Enable support for DS4510 CPU supervisor"
+	help
+	  Enable support for the Maxim DS4510 CPU supervisor. It has an
+	  integrated 64-byte EEPROM, four programmable non-volatile I/O pins
+	  and a configurable timer for the supervisor function. The device is
+	  connected over I2C.
+
 config FSL_SEC_MON
 	bool "Enable FSL SEC_MON Driver"
 	help
@@ -90,6 +119,14 @@ config MXC_OCOTP
 	  Programmable memory pages that are stored on the some
 	  Freescale i.MX processors.
 
+config NUVOTON_NCT6102D
+	bool "Enable Nuvoton NCT6102D Super I/O driver"
+	help
+	  If you say Y here, you will get support for the Nuvoton
+	  NCT6102D Super I/O driver. This can be used to enable or
+	  disable the legacy UART, the watchdog or other devices
+	  in the Nuvoton Super IO chips on X86 platforms.
+
 config PWRSEQ
 	bool "Enable power-sequencing drivers"
 	depends on DM
@@ -121,14 +158,33 @@ config PCA9551_I2C_ADDR
 	help
 	  The I2C address of the PCA9551 LED controller.
 
-config RESET
-	bool "Enable support for reset drivers"
-	depends on DM
+config STM32_RCC
+	bool "Enable RCC driver for the STM32 SoC's family"
+	depends on STM32 && MISC
+	help
+	  Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
+	  block) is responsible of the management of the clock and reset
+	  generation.
+	  This driver is similar to an MFD driver in the Linux kernel.
+
+config TEGRA_CAR
+	bool "Enable support for the Tegra CAR driver"
+	depends on TEGRA_NO_BPMP
 	help
-	  Enable reset drivers which can be used to reset the CPU or board.
-	  Each driver can provide a reset method which will be called to
-	  effect a reset. The uclass will try all available drivers when
-	  reset_walk() is called.
+	  The Tegra CAR (Clock and Reset Controller) is a HW module that
+	  controls almost all clocks and resets in a Tegra SoC.
+
+config TEGRA186_BPMP
+	bool "Enable support for the Tegra186 BPMP driver"
+	depends on TEGRA186
+	help
+	  The Tegra BPMP (Boot and Power Management Processor) is a separate
+	  auxiliary CPU embedded into Tegra to perform power management work,
+	  and controls related features such as clocks, resets, power domains,
+	  PMIC I2C bus, etc. This driver provides the core low-level
+	  communication path by which feature-specific drivers (such as clock)
+	  can make requests to the BPMP. This driver is similar to an MFD
+	  driver in the Linux kernel.
 
 config WINBOND_W83627
 	bool "Enable Winbond Super I/O driver"
@@ -144,4 +200,62 @@ config QFW
 	  Hidden option to enable QEMU fw_cfg interface. This will be selected by
 	  either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
 
+config I2C_EEPROM
+	bool "Enable driver for generic I2C-attached EEPROMs"
+	depends on MISC
+	help
+	  Enable a generic driver for EEPROMs attached via I2C.
+
+
+config SPL_I2C_EEPROM
+	bool "Enable driver for generic I2C-attached EEPROMs for SPL"
+	depends on MISC && SPL && SPL_DM
+	help
+	  This option is an SPL-variant of the I2C_EEPROM option.
+	  See the help of I2C_EEPROM for details.
+
+if I2C_EEPROM
+
+config SYS_I2C_EEPROM_ADDR
+	hex "Chip address of the EEPROM device"
+	default 0
+
+config SYS_I2C_EEPROM_BUS
+	int "I2C bus of the EEPROM device."
+	default 0
+
+config SYS_EEPROM_SIZE
+	int "Size in bytes of the EEPROM device"
+	default 256
+
+config SYS_EEPROM_PAGE_WRITE_BITS
+	int "Number of bits used to address bytes in a single page"
+	default 0
+	help
+	  The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
+	  A 64 byte page, for example would require six bits.
+
+config SYS_EEPROM_PAGE_WRITE_DELAY_MS
+	int "Number of milliseconds to delay between page writes"
+	default 0
+
+config SYS_I2C_EEPROM_ADDR_LEN
+	int "Length in bytes of the EEPROM memory array address"
+	default 1
+	help
+	  Note: This is NOT the chip address length!
+
+config SYS_I2C_EEPROM_ADDR_OVERFLOW
+	hex "EEPROM Address Overflow"
+	default 0
+	help
+	  EEPROM chips that implement "address overflow" are ones
+	  like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+	  address and the extra bits end up in the "chip address" bit
+	  slots. This makes a 24WC08 (1Kbyte) chip look like four 256
+	  byte chips.
+
+endif
+
+
 endmenu