X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fmisc%2Fmxc_ocotp.c;h=8662e82cfa118a9b21b7481dea84325f174e19d8;hb=48f54a2d749517db1c57749c28832df8ea9f8b72;hp=6b8566c8d0254f7cfadd66a20d64e04f901bf82b;hpb=cbe7706ab8aab06c18edaa9b120371f9c8012728;p=u-boot

diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 6b8566c8d0..8662e82cfa 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -18,6 +18,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/mach-imx/sys_proto.h>
 
 #define BO_CTRL_WR_UNLOCK		16
 #define BM_CTRL_WR_UNLOCK		0xffff0000
@@ -28,6 +29,14 @@
 #ifdef CONFIG_MX7
 #define BM_CTRL_ADDR                    0x0000000f
 #define BM_CTRL_RELOAD                  0x00000400
+#elif defined(CONFIG_MX7ULP)
+#define BM_CTRL_ADDR                    0x000000FF
+#define BM_CTRL_RELOAD                  0x00000400
+#define BM_OUT_STATUS_DED				0x00000400
+#define BM_OUT_STATUS_LOCKED			0x00000800
+#define BM_OUT_STATUS_PROGFAIL			0x00001000
+#elif defined(CONFIG_MX8M)
+#define BM_CTRL_ADDR			0x000000ff
 #else
 #define BM_CTRL_ADDR			0x0000007f
 #endif
@@ -61,22 +70,30 @@
 #define FUSE_BANK_SIZE	0x80
 #ifdef CONFIG_MX6SL
 #define FUSE_BANKS	8
+#elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
+#define FUSE_BANKS	9
 #else
 #define FUSE_BANKS	16
 #endif
 #elif defined CONFIG_MX7
 #define FUSE_BANK_SIZE	0x40
 #define FUSE_BANKS	16
+#elif defined(CONFIG_MX7ULP)
+#define FUSE_BANK_SIZE	0x80
+#define FUSE_BANKS	31
+#elif defined(CONFIG_MX8M)
+#define FUSE_BANK_SIZE	0x40
+#define FUSE_BANKS	64
 #else
 #error "Unsupported architecture\n"
 #endif
 
 #if defined(CONFIG_MX6)
-#include <asm/arch/sys_proto.h>
 
 /*
  * There is a hole in shadow registers address map of size 0x100
- * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL.
+ * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX,
+ * iMX6UL, i.MX6ULL and i.MX6SLL.
  * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
  * we should account for this hole in address space.
  *
@@ -95,9 +112,12 @@ u32 fuse_bank_physical(int index)
 {
 	u32 phy_index;
 
-	if (is_mx6sl()) {
+	if (is_mx6sl() || is_mx7ulp()) {
 		phy_index = index;
-	} else if (is_mx6ul()) {
+	} else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
+		if ((is_mx6ull() || is_mx6sll()) && index == 8)
+			index = 7;
+
 		if (index >= 6)
 			phy_index = fuse_bank_physical(5) + (index - 6) + 3;
 		else
@@ -112,11 +132,27 @@ u32 fuse_bank_physical(int index)
 	}
 	return phy_index;
 }
+
+u32 fuse_word_physical(u32 bank, u32 word_index)
+{
+	if (is_mx6ull() || is_mx6sll()) {
+		if (bank == 8)
+			word_index = word_index + 4;
+	}
+
+	return word_index;
+}
 #else
 u32 fuse_bank_physical(int index)
 {
 	return index;
 }
+
+u32 fuse_word_physical(u32 bank, u32 word_index)
+{
+	return word_index;
+}
+
 #endif
 
 static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
@@ -142,6 +178,14 @@ static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
 		return -EINVAL;
 	}
 
+	if (is_mx6ull() || is_mx6sll()) {
+		if ((bank == 7 || bank == 8) &&
+		    word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) {
+			printf("mxc_ocotp %s(): Invalid argument\n", caller);
+			return -EINVAL;
+		}
+	}
+
 	enable_ocotp_clk(1);
 
 	wait_busy(*regs, 1);
@@ -157,6 +201,10 @@ static int finish_access(struct ocotp_regs *regs, const char *caller)
 	err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
 	clear_error(regs);
 
+#ifdef CONFIG_MX7ULP
+	/* Need to power down the OTP memory */
+	writel(1, &regs->pdn);
+#endif
 	if (err) {
 		printf("mxc_ocotp %s(): Access protect error\n", caller);
 		return -EIO;
@@ -176,15 +224,24 @@ int fuse_read(u32 bank, u32 word, u32 *val)
 	struct ocotp_regs *regs;
 	int ret;
 	u32 phy_bank;
+	u32 phy_word;
 
 	ret = prepare_read(&regs, bank, word, val, __func__);
 	if (ret)
 		return ret;
 
 	phy_bank = fuse_bank_physical(bank);
+	phy_word = fuse_word_physical(bank, word);
 
-	*val = readl(&regs->bank[phy_bank].fuse_regs[word << 2]);
+	*val = readl(&regs->bank[phy_bank].fuse_regs[phy_word << 2]);
 
+#ifdef CONFIG_MX7ULP
+	if (readl(&regs->out_status) & BM_OUT_STATUS_DED) {
+		writel(BM_OUT_STATUS_DED, &regs->out_status_clr);
+		printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
+		return -EIO;
+	}
+#endif
 	return finish_access(regs, __func__);
 }
 
@@ -206,6 +263,12 @@ static void set_timing(struct ocotp_regs *regs)
 	clrsetbits_le32(&regs->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG,
 			timing);
 }
+#elif defined(CONFIG_MX7ULP)
+static void set_timing(struct ocotp_regs *regs)
+{
+	/* No timing set for MX7ULP */
+}
+
 #else
 static void set_timing(struct ocotp_regs *regs)
 {
@@ -236,8 +299,16 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
 	u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
 #ifdef CONFIG_MX7
 	u32 addr = bank;
+#elif defined CONFIG_MX8M
+	u32 addr = bank << 2 | word;
 #else
-	u32 addr = bank << 3 | word;
+	u32 addr;
+	/* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
+	if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) {
+		bank = bank - 1;
+		word += 4;
+	}
+	addr = bank << 3 | word;
 #endif
 
 	set_timing(regs);
@@ -264,12 +335,37 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
 	*val = readl(&regs->read_fuse_data);
 #endif
 
+#ifdef CONFIG_MX7ULP
+	if (readl(&regs->out_status) & BM_OUT_STATUS_DED) {
+		writel(BM_OUT_STATUS_DED, &regs->out_status_clr);
+		printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
+		return -EIO;
+	}
+#endif
+
 	return finish_access(regs, __func__);
 }
 
 static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
 				const char *caller)
 {
+#ifdef CONFIG_MX7ULP
+	u32 val;
+	int ret;
+
+	/* Only bank 0 and 1 are redundancy mode, others are ECC mode */
+	if (bank != 0 && bank != 1) {
+		ret = fuse_sense(bank, word, &val);
+		if (ret)
+			return ret;
+
+		if (val != 0) {
+			printf("mxc_ocotp: The word has been programmed, no more write\n");
+			return -EPERM;
+		}
+	}
+#endif
+
 	return prepare_access(regs, bank, word, true, caller);
 }
 
@@ -317,6 +413,14 @@ int fuse_prog(u32 bank, u32 word, u32 val)
 #endif
 	udelay(WRITE_POSTAMBLE_US);
 
+#ifdef CONFIG_MX7ULP
+	if (readl(&regs->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
+		writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), &regs->out_status_clr);
+		printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
+		return -EIO;
+	}
+#endif
+
 	return finish_access(regs, __func__);
 }
 
@@ -325,14 +429,24 @@ int fuse_override(u32 bank, u32 word, u32 val)
 	struct ocotp_regs *regs;
 	int ret;
 	u32 phy_bank;
+	u32 phy_word;
 
 	ret = prepare_write(&regs, bank, word, __func__);
 	if (ret)
 		return ret;
 
 	phy_bank = fuse_bank_physical(bank);
+	phy_word = fuse_word_physical(bank, word);
+
+	writel(val, &regs->bank[phy_bank].fuse_regs[phy_word << 2]);
 
-	writel(val, &regs->bank[phy_bank].fuse_regs[word << 2]);
+#ifdef CONFIG_MX7ULP
+	if (readl(&regs->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
+		writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), &regs->out_status_clr);
+		printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
+		return -EIO;
+	}
+#endif
 
 	return finish_access(regs, __func__);
 }