X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fmisc%2Fmxc_ocotp.c;h=8a100c19bdcc2b3b3c814caf66e01f15f05965ee;hb=2cb5d67c1aceb758033954cc06382367ac89e6ac;hp=d9b02c78e2c5e63541fd1fe9dc2f0a6a4b00147b;hpb=42c91c10c52a3f3512ad5c5e906bc118349bbff5;p=u-boot diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index d9b02c78e2..8a100c19bd 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -14,10 +14,11 @@ #include #include -#include +#include #include #include #include +#include #define BO_CTRL_WR_UNLOCK 16 #define BM_CTRL_WR_UNLOCK 0xffff0000 @@ -57,6 +58,89 @@ #define WRITE_POSTAMBLE_US 2 +#if defined(CONFIG_MX6) || defined(CONFIG_VF610) +#define FUSE_BANK_SIZE 0x80 +#ifdef CONFIG_MX6SL +#define FUSE_BANKS 8 +#elif defined(CONFIG_MX6ULL) +#define FUSE_BANKS 9 +#else +#define FUSE_BANKS 16 +#endif +#elif defined CONFIG_MX7 +#define FUSE_BANK_SIZE 0x40 +#define FUSE_BANKS 16 +#else +#error "Unsupported architecture\n" +#endif + +#if defined(CONFIG_MX6) + +/* + * There is a hole in shadow registers address map of size 0x100 + * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX, + * iMX6UL and i.MX6ULL. + * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, + * we should account for this hole in address space. + * + * Similar hole exists between bank 14 and bank 15 of size + * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. + * Note: iMX6SL has only 0-7 banks and there is no hole. + * Note: iMX6UL doesn't have this one. + * + * This function is to covert user input to physical bank index. + * Only needed when read fuse, because we use register offset, so + * need to calculate real register offset. + * When write, no need to consider hole, always use the bank/word + * index from fuse map. + */ +u32 fuse_bank_physical(int index) +{ + u32 phy_index; + + if (is_mx6sl()) { + phy_index = index; + } else if (is_mx6ul() || is_mx6ull()) { + if (is_mx6ull() && index == 8) + index = 7; + + if (index >= 6) + phy_index = fuse_bank_physical(5) + (index - 6) + 3; + else + phy_index = index; + } else { + if (index >= 15) + phy_index = fuse_bank_physical(14) + (index - 15) + 2; + else if (index >= 6) + phy_index = fuse_bank_physical(5) + (index - 6) + 3; + else + phy_index = index; + } + return phy_index; +} + +u32 fuse_word_physical(u32 bank, u32 word_index) +{ + if (is_mx6ull()) { + if (bank == 8) + word_index = word_index + 4; + } + + return word_index; +} +#else +u32 fuse_bank_physical(int index) +{ + return index; +} + +u32 fuse_word_physical(u32 bank, u32 word_index) +{ + return word_index; +} + +#endif + static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us) { while (readl(®s->ctrl) & BM_CTRL_BUSY) @@ -73,13 +157,21 @@ static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word, { *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR; - if (bank >= ARRAY_SIZE((*regs)->bank) || - word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || - !assert) { + if (bank >= FUSE_BANKS || + word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || + !assert) { printf("mxc_ocotp %s(): Invalid argument\n", caller); return -EINVAL; } + if (is_mx6ull()) { + if ((bank == 7 || bank == 8) && + word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) { + printf("mxc_ocotp %s(): Invalid argument on 6ULL\n", caller); + return -EINVAL; + } + } + enable_ocotp_clk(1); wait_busy(*regs, 1); @@ -113,12 +205,17 @@ int fuse_read(u32 bank, u32 word, u32 *val) { struct ocotp_regs *regs; int ret; + u32 phy_bank; + u32 phy_word; ret = prepare_read(®s, bank, word, val, __func__); if (ret) return ret; - *val = readl(®s->bank[bank].fuse_regs[word << 2]); + phy_bank = fuse_bank_physical(bank); + phy_word = fuse_word_physical(bank, word); + + *val = readl(®s->bank[phy_bank].fuse_regs[phy_word << 2]); return finish_access(regs, __func__); } @@ -172,7 +269,13 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word, #ifdef CONFIG_MX7 u32 addr = bank; #else - u32 addr = bank << 3 | word; + u32 addr; + /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */ + if ((is_mx6ull()) && (bank > 7)) { + bank = bank - 1; + word += 4; + } + addr = bank << 3 | word; #endif set_timing(regs); @@ -259,12 +362,17 @@ int fuse_override(u32 bank, u32 word, u32 val) { struct ocotp_regs *regs; int ret; + u32 phy_bank; + u32 phy_word; ret = prepare_write(®s, bank, word, __func__); if (ret) return ret; - writel(val, ®s->bank[bank].fuse_regs[word << 2]); + phy_bank = fuse_bank_physical(bank); + phy_word = fuse_word_physical(bank, word); + + writel(val, ®s->bank[phy_bank].fuse_regs[phy_word << 2]); return finish_access(regs, __func__); }