X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fmmc%2Farm_pl180_mmci.h;h=f23bd391eed1c5ce91af4ee59a8c992c69ff65e9;hb=9b081d8893c4fce3451e3a5a4d5ac5a9960874ae;hp=42fbe3e3860f2b412cd1bf9d1473b29d20deb897;hpb=909e9bf3ae6195ac6d52f9e453fba2be8e7e947f;p=u-boot

diff --git a/drivers/mmc/arm_pl180_mmci.h b/drivers/mmc/arm_pl180_mmci.h
index 42fbe3e386..f23bd391ee 100644
--- a/drivers/mmc/arm_pl180_mmci.h
+++ b/drivers/mmc/arm_pl180_mmci.h
@@ -7,26 +7,14 @@
  * Author: Martin Lundholm <martin.xa.lundholm@stericsson.com>
  * Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __ARM_PL180_MMCI_H__
 #define __ARM_PL180_MMCI_H__
 
-int arm_pl180_mmci_init(void);
+/* need definition of struct mmc_config */
+#include <mmc.h>
 
 #define COMMAND_REG_DELAY	300
 #define DATA_REG_DELAY		1000
@@ -59,8 +47,13 @@ int arm_pl180_mmci_init(void);
 #define SDI_CLKCR_WIDBUS_MASK	0x00001800
 #define SDI_CLKCR_WIDBUS_1	0x00000000
 #define SDI_CLKCR_WIDBUS_4	0x00000800
+/* V2 only */
+#define SDI_CLKCR_WIDBUS_8	0x00001000
+#define SDI_CLKCR_NEDGE		0x00002000
+#define SDI_CLKCR_HWFC_EN	0x00004000
 
-#define SDI_CLKCR_CLKDIV_INIT	0x000000C6 /* MCLK/(2*(0xC6+1)) => 505KHz */
+#define SDI_CLKCR_CLKDIV_INIT_V1 0x000000C6 /* MCLK/(2*(0xC6+1)) => 505KHz */
+#define SDI_CLKCR_CLKDIV_INIT_V2 0x000000FD
 
 /* SDI command register bits */
 #define SDI_CMD_CMDINDEX_MASK	0x000000FF
@@ -144,6 +137,8 @@ int arm_pl180_mmci_init(void);
 #define SDI_DCTRL_DBOOTMODEEN	0x00002000
 #define SDI_DCTRL_BUSYMODE	0x00004000
 #define SDI_DCTRL_DDR_MODE	0x00008000
+#define SDI_DCTRL_DBLOCKSIZE_V2_MASK   0x7fff0000
+#define SDI_DCTRL_DBLOCKSIZE_V2_SHIFT  16
 
 #define SDI_FIFO_BURST_SIZE	8
 
@@ -180,4 +175,21 @@ struct sdi_registers {
 	u32 pcell_id3;		/* 0xFFC*/
 };
 
+struct pl180_mmc_host {
+	struct sdi_registers *base;
+	char name[32];
+	unsigned int b_max;
+	unsigned int voltages;
+	unsigned int caps;
+	unsigned int clock_in;
+	unsigned int clock_min;
+	unsigned int clock_max;
+	unsigned int clkdiv_init;
+	unsigned int pwr_init;
+	int version2;
+	struct mmc_config cfg;
+};
+
+int arm_pl180_mmci_init(struct pl180_mmc_host *);
+
 #endif