X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fmmc%2Fdw_mmc.c;h=074f86c502c0d2aed6eb1c2ffeedfe5730fdbc81;hb=1221ce459d04a428f8880f58581f671b736c3c27;hp=0df30bc04530e162603f3f7ae801518f775ae5ef;hpb=e82abaeb7f2a0833fccf90460c48b9f2100258f8;p=u-boot diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 0df30bc045..074f86c502 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -8,10 +8,11 @@ #include #include +#include #include +#include #include #include -#include #define PAGE_SIZE 4096 @@ -38,7 +39,7 @@ static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, desc->flags = desc0; desc->cnt = desc1; desc->addr = desc2; - desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac); + desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac); } static void dwmci_prepare_data(struct dwmci_host *host, @@ -56,7 +57,7 @@ static void dwmci_prepare_data(struct dwmci_host *host, dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); data_start = (ulong)cur_idmac; - dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac); + dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac); do { flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; @@ -68,7 +69,7 @@ static void dwmci_prepare_data(struct dwmci_host *host, cnt = data->blocksize * 8; dwmci_set_idma_desc(cur_idmac, flags, cnt, - (u32)bounce_buffer + (i * PAGE_SIZE)); + (ulong)bounce_buffer + (i * PAGE_SIZE)); if (blk_cnt <= 8) break; @@ -92,6 +93,85 @@ static void dwmci_prepare_data(struct dwmci_host *host, dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); } +static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) +{ + int ret = 0; + u32 timeout = 240000; + u32 mask, size, i, len = 0; + u32 *buf = NULL; + ulong start = get_timer(0); + u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> + RX_WMARK_SHIFT) + 1) * 2; + + size = data->blocksize * data->blocks / 4; + if (data->flags == MMC_DATA_READ) + buf = (unsigned int *)data->dest; + else + buf = (unsigned int *)data->src; + + for (;;) { + mask = dwmci_readl(host, DWMCI_RINTSTS); + /* Error during data transfer. */ + if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { + debug("%s: DATA ERROR!\n", __func__); + ret = -EINVAL; + break; + } + + if (host->fifo_mode && size) { + len = 0; + if (data->flags == MMC_DATA_READ && + (mask & DWMCI_INTMSK_RXDR)) { + while (size) { + len = dwmci_readl(host, DWMCI_STATUS); + len = (len >> DWMCI_FIFO_SHIFT) & + DWMCI_FIFO_MASK; + len = min(size, len); + for (i = 0; i < len; i++) + *buf++ = + dwmci_readl(host, DWMCI_DATA); + size = size > len ? (size - len) : 0; + } + dwmci_writel(host, DWMCI_RINTSTS, + DWMCI_INTMSK_RXDR); + } else if (data->flags == MMC_DATA_WRITE && + (mask & DWMCI_INTMSK_TXDR)) { + while (size) { + len = dwmci_readl(host, DWMCI_STATUS); + len = fifo_depth - ((len >> + DWMCI_FIFO_SHIFT) & + DWMCI_FIFO_MASK); + len = min(size, len); + for (i = 0; i < len; i++) + dwmci_writel(host, DWMCI_DATA, + *buf++); + size = size > len ? (size - len) : 0; + } + dwmci_writel(host, DWMCI_RINTSTS, + DWMCI_INTMSK_TXDR); + } + } + + /* Data arrived correctly. */ + if (mask & DWMCI_INTMSK_DTO) { + ret = 0; + break; + } + + /* Check for timeout. */ + if (get_timer(start) > timeout) { + debug("%s: Timeout waiting for data!\n", + __func__); + ret = -ETIMEDOUT; + break; + } + } + + dwmci_writel(host, DWMCI_RINTSTS, mask); + + return ret; +} + static int dwmci_set_transfer_mode(struct dwmci_host *host, struct mmc_data *data) { @@ -104,40 +184,54 @@ static int dwmci_set_transfer_mode(struct dwmci_host *host, return mode; } +#ifdef CONFIG_DM_MMC_OPS +static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { +#endif struct dwmci_host *host = mmc->priv; ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, data ? DIV_ROUND_UP(data->blocks, 8) : 0); - int flags = 0, i; - unsigned int timeout = 100000; - u32 retry = 10000; + int ret = 0, flags = 0, i; + unsigned int timeout = 500; + u32 retry = 100000; u32 mask, ctrl; ulong start = get_timer(0); struct bounce_buffer bbstate; while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { if (get_timer(start) > timeout) { - printf("Timeout on data busy\n"); - return TIMEOUT; + debug("%s: Timeout on data busy\n", __func__); + return -ETIMEDOUT; } } dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); if (data) { - if (data->flags == MMC_DATA_READ) { - bounce_buffer_start(&bbstate, (void*)data->dest, - data->blocksize * - data->blocks, GEN_BB_WRITE); + if (host->fifo_mode) { + dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); + dwmci_writel(host, DWMCI_BYTCNT, + data->blocksize * data->blocks); + dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); } else { - bounce_buffer_start(&bbstate, (void*)data->src, - data->blocksize * - data->blocks, GEN_BB_READ); + if (data->flags == MMC_DATA_READ) { + bounce_buffer_start(&bbstate, (void*)data->dest, + data->blocksize * + data->blocks, GEN_BB_WRITE); + } else { + bounce_buffer_start(&bbstate, (void*)data->src, + data->blocksize * + data->blocks, GEN_BB_READ); + } + dwmci_prepare_data(host, data, cur_idmac, + bbstate.bounce_buffer); } - dwmci_prepare_data(host, data, cur_idmac, - bbstate.bounce_buffer); } dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); @@ -177,15 +271,25 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } } - if (i == retry) - return TIMEOUT; + if (i == retry) { + debug("%s: Timeout.\n", __func__); + return -ETIMEDOUT; + } if (mask & DWMCI_INTMSK_RTO) { - debug("Response Timeout..\n"); - return TIMEOUT; + /* + * Timeout here is not necessarily fatal. (e)MMC cards + * will splat here when they receive CMD55 as they do + * not support this command and that is exactly the way + * to tell them apart from SD cards. Thus, this output + * below shall be debug(). eMMC cards also do not favor + * CMD8, please keep that in mind. + */ + debug("%s: Response Timeout.\n", __func__); + return -ETIMEDOUT; } else if (mask & DWMCI_INTMSK_RE) { - debug("Response Error..\n"); - return -1; + debug("%s: Response Error.\n", __func__); + return -EIO; } @@ -201,26 +305,20 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } if (data) { - do { - mask = dwmci_readl(host, DWMCI_RINTSTS); - if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { - debug("DATA ERROR!\n"); - return -1; - } - } while (!(mask & DWMCI_INTMSK_DTO)); - - dwmci_writel(host, DWMCI_RINTSTS, mask); - - ctrl = dwmci_readl(host, DWMCI_CTRL); - ctrl &= ~(DWMCI_DMA_EN); - dwmci_writel(host, DWMCI_CTRL, ctrl); - - bounce_buffer_stop(&bbstate); + ret = dwmci_data_transfer(host, data); + + /* only dma mode need it */ + if (!host->fifo_mode) { + ctrl = dwmci_readl(host, DWMCI_CTRL); + ctrl &= ~(DWMCI_DMA_EN); + dwmci_writel(host, DWMCI_CTRL, ctrl); + bounce_buffer_stop(&bbstate); + } } udelay(100); - return 0; + return ret; } static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) @@ -232,16 +330,16 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) if ((freq == host->clock) || (freq == 0)) return 0; /* - * If host->get_mmc_clk didn't define, + * If host->get_mmc_clk isn't defined, * then assume that host->bus_hz is source clock value. - * host->bus_hz should be set from user. + * host->bus_hz should be set by user. */ if (host->get_mmc_clk) - sclk = host->get_mmc_clk(host); + sclk = host->get_mmc_clk(host, freq); else if (host->bus_hz) sclk = host->bus_hz; else { - printf("Didn't get source clock value..\n"); + debug("%s: Didn't get source clock value.\n", __func__); return -EINVAL; } @@ -260,7 +358,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) do { status = dwmci_readl(host, DWMCI_CMD); if (timeout-- < 0) { - printf("TIMEOUT error!!\n"); + debug("%s: Timeout!\n", __func__); return -ETIMEDOUT; } } while (status & DWMCI_CMD_START); @@ -275,7 +373,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) do { status = dwmci_readl(host, DWMCI_CMD); if (timeout-- < 0) { - printf("TIMEOUT error!!\n"); + debug("%s: Timeout!\n", __func__); return -ETIMEDOUT; } } while (status & DWMCI_CMD_START); @@ -285,12 +383,18 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) return 0; } +#ifdef CONFIG_DM_MMC_OPS +static int dwmci_set_ios(struct udevice *dev) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else static void dwmci_set_ios(struct mmc *mmc) { +#endif struct dwmci_host *host = (struct dwmci_host *)mmc->priv; u32 ctype, regs; - debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock); + debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); dwmci_setup_bus(host, mmc->clock); switch (mmc->bus_width) { @@ -308,15 +412,18 @@ static void dwmci_set_ios(struct mmc *mmc) dwmci_writel(host, DWMCI_CTYPE, ctype); regs = dwmci_readl(host, DWMCI_UHS_REG); - if (mmc->card_caps & MMC_MODE_DDR_52MHz) + if (mmc->ddr_mode) regs |= DWMCI_DDR_MODE; else - regs &= DWMCI_DDR_MODE; + regs &= ~DWMCI_DDR_MODE; dwmci_writel(host, DWMCI_UHS_REG, regs); if (host->clksel) host->clksel(host); +#ifdef CONFIG_DM_MMC_OPS + return 0; +#endif } static int dwmci_init(struct mmc *mmc) @@ -329,8 +436,8 @@ static int dwmci_init(struct mmc *mmc) dwmci_writel(host, DWMCI_PWREN, 1); if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { - debug("%s[%d] Fail-reset!!\n",__func__,__LINE__); - return -1; + debug("%s[%d] Fail-reset!!\n", __func__, __LINE__); + return -EIO; } /* Enumerate at 400KHz */ @@ -344,9 +451,15 @@ static int dwmci_init(struct mmc *mmc) dwmci_writel(host, DWMCI_IDINTEN, 0); dwmci_writel(host, DWMCI_BMOD, 1); - if (host->fifoth_val) { - dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); + if (!host->fifoth_val) { + uint32_t fifo_size; + + fifo_size = dwmci_readl(host, DWMCI_FIFOTH); + fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; + host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) | + TX_WMARK(fifo_size / 2); } + dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); dwmci_writel(host, DWMCI_CLKENA, 0); dwmci_writel(host, DWMCI_CLKSRC, 0); @@ -354,33 +467,63 @@ static int dwmci_init(struct mmc *mmc) return 0; } +#ifdef CONFIG_DM_MMC_OPS +int dwmci_probe(struct udevice *dev) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); + + return dwmci_init(mmc); +} + +const struct dm_mmc_ops dm_dwmci_ops = { + .send_cmd = dwmci_send_cmd, + .set_ios = dwmci_set_ios, +}; + +#else static const struct mmc_ops dwmci_ops = { .send_cmd = dwmci_send_cmd, .set_ios = dwmci_set_ios, .init = dwmci_init, }; +#endif -int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) +void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, + uint caps, u32 max_clk, u32 min_clk) { - host->cfg.name = host->name; - host->cfg.ops = &dwmci_ops; - host->cfg.f_min = min_clk; - host->cfg.f_max = max_clk; + cfg->name = name; +#ifndef CONFIG_DM_MMC_OPS + cfg->ops = &dwmci_ops; +#endif + cfg->f_min = min_clk; + cfg->f_max = max_clk; - host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - host->cfg.host_caps = host->caps; + cfg->host_caps = caps; - if (host->buswidth == 8) { - host->cfg.host_caps |= MMC_MODE_8BIT; - host->cfg.host_caps &= ~MMC_MODE_4BIT; + if (buswidth == 8) { + cfg->host_caps |= MMC_MODE_8BIT; + cfg->host_caps &= ~MMC_MODE_4BIT; } else { - host->cfg.host_caps |= MMC_MODE_4BIT; - host->cfg.host_caps &= ~MMC_MODE_8BIT; + cfg->host_caps |= MMC_MODE_4BIT; + cfg->host_caps &= ~MMC_MODE_8BIT; } - host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC; + cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; - host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; +} + +#ifdef CONFIG_BLK +int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) +{ + return mmc_bind(dev, mmc, cfg); +} +#else +int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) +{ + dwmci_setup_cfg(&host->cfg, host->name, host->buswidth, host->caps, + max_clk, min_clk); host->mmc = mmc_create(&host->cfg, host); if (host->mmc == NULL) @@ -388,3 +531,4 @@ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) return 0; } +#endif