X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fmmc%2Fexynos_dw_mmc.c;h=b3e5c5e5e09b5db5d04bfac1b8bd3093b9d3d655;hb=7f673c99c2d8d1aa21996c5b914f06d784b080ca;hp=a0f1511cb6f308de404defef63383016bfd2d932;hpb=85b8c5c4bf80025de4632ae6c9a8a606e51508a4;p=u-boot

diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index a0f1511cb6..b3e5c5e5e0 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -34,6 +34,19 @@ unsigned int exynos_dwmci_get_clk(int dev_index)
 	return get_mmc_clk(dev_index);
 }
 
+static void exynos_dwmci_board_init(struct dwmci_host *host)
+{
+	if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
+		dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
+		dwmci_writel(host, EMMCP_SEND0, 0);
+		dwmci_writel(host, EMMCP_CTRL0,
+			     MPSCTRL_SECURE_READ_BIT |
+			     MPSCTRL_SECURE_WRITE_BIT |
+			     MPSCTRL_NON_SECURE_READ_BIT |
+			     MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
+	}
+}
+
 /*
  * This function adds the mmc channel to be registered with mmc core.
  * index -	mmc channel number.
@@ -65,6 +78,7 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
 #ifdef CONFIG_EXYNOS5420
 	host->quirks = DWMCI_QUIRK_DISABLE_SMU;
 #endif
+	host->board_init = exynos_dwmci_board_init;
 
 	if (clksel) {
 		host->clksel_val = clksel;