X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fmmc%2Fsocfpga_dw_mmc.c;h=43a7e7ea3247bb1c3aa91c2da03a317310c723b3;hb=0c2b6dffb7fcd6ef028020587a030b6bef154a0e;hp=bc53a5da272582429a833e79653f2a7632458da7;hpb=707acd01ded3c60a4e277f7c5432d397897b4dfd;p=u-boot

diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index bc53a5da27..43a7e7ea32 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -5,64 +5,124 @@
  */
 
 #include <common.h>
-#include <malloc.h>
-#include <dwmmc.h>
-#include <asm/arch/dwmmc.h>
 #include <asm/arch/clock_manager.h>
+#include <asm/arch/dwmmc.h>
 #include <asm/arch/system_manager.h>
+#include <dm.h>
+#include <dwmmc.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <linux/err.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 static const struct socfpga_clock_manager *clock_manager_base =
 		(void *)SOCFPGA_CLKMGR_ADDRESS;
 static const struct socfpga_system_manager *system_manager_base =
 		(void *)SOCFPGA_SYSMGR_ADDRESS;
 
-static char *SOCFPGA_NAME = "SOCFPGA DWMMC";
+/* socfpga implmentation specific driver private data */
+struct dwmci_socfpga_priv_data {
+	struct dwmci_host	host;
+	unsigned int		drvsel;
+	unsigned int		smplsel;
+};
 
 static void socfpga_dwmci_clksel(struct dwmci_host *host)
 {
-	unsigned int drvsel;
-	unsigned int smplsel;
+	struct dwmci_socfpga_priv_data *priv = host->priv;
+	u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
+			 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
 
 	/* Disable SDMMC clock. */
-	clrbits_le32(&clock_manager_base->per_pll_en,
+	clrbits_le32(&clock_manager_base->per_pll.en,
 		CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
 
-	/* Configures drv_sel and smpl_sel */
-	drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL;
-	smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL;
-
-	debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel);
-	writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel),
-		&system_manager_base->sdmmcgrp_ctrl);
+	debug("%s: drvsel %d smplsel %d\n", __func__,
+	      priv->drvsel, priv->smplsel);
+	writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
 
 	debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
 		readl(&system_manager_base->sdmmcgrp_ctrl));
 
 	/* Enable SDMMC clock */
-	setbits_le32(&clock_manager_base->per_pll_en,
+	setbits_le32(&clock_manager_base->per_pll.en,
 		CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
 }
 
-int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
+static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
 {
-	struct dwmci_host *host = NULL;
-	host = calloc(sizeof(struct dwmci_host), 1);
-	if (!host) {
-		printf("dwmci_host calloc fail!\n");
-		return -1;
+	/* FIXME: probe from DT eventually too/ */
+	const unsigned long clk = cm_get_mmc_controller_clk_hz();
+
+	struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
+	struct dwmci_host *host = &priv->host;
+	int fifo_depth;
+
+	if (clk == 0) {
+		printf("DWMMC: MMC clock is zero!");
+		return -EINVAL;
 	}
 
-	host->name = SOCFPGA_NAME;
-	host->ioaddr = (void *)regbase;
-	host->buswidth = bus_width;
+	fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+				    "fifo-depth", 0);
+	if (fifo_depth < 0) {
+		printf("DWMMC: Can't get FIFO depth\n");
+		return -EINVAL;
+	}
+
+	host->name = dev->name;
+	host->ioaddr = (void *)dev_get_addr(dev);
+	host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+					"bus-width", 4);
 	host->clksel = socfpga_dwmci_clksel;
-	host->dev_index = index;
-	/* fixed clock divide by 4 which due to the SDMMC wrapper */
-	host->bus_hz = CONFIG_SOCFPGA_DWMMC_BUS_HZ;
+
+	/*
+	 * TODO(sjg@chromium.org): Remove the need for this hack.
+	 * We only have one dwmmc block on gen5 SoCFPGA.
+	 */
+	host->dev_index = 0;
+	/* Fixed clock divide by 4 which due to the SDMMC wrapper */
+	host->bus_hz = clk;
 	host->fifoth_val = MSIZE(0x2) |
-		RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) |
-		TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2);
+		RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
+	priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+				       "drvsel", 3);
+	priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+					"smplsel", 0);
+	host->priv = priv;
+
+	return 0;
+}
 
-	return add_dwmci(host, host->bus_hz, 400000);
+static int socfpga_dwmmc_probe(struct udevice *dev)
+{
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+	struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
+	struct dwmci_host *host = &priv->host;
+	int ret;
+
+	ret = add_dwmci(host, host->bus_hz, 400000);
+	if (ret)
+		return ret;
+
+	upriv->mmc = host->mmc;
+
+	return 0;
 }
 
+static const struct udevice_id socfpga_dwmmc_ids[] = {
+	{ .compatible = "altr,socfpga-dw-mshc" },
+	{ }
+};
+
+U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
+	.name		= "socfpga_dwmmc",
+	.id		= UCLASS_MMC,
+	.of_match	= socfpga_dwmmc_ids,
+	.ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
+	.probe		= socfpga_dwmmc_probe,
+	.priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
+};