X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fmmc%2Fsocfpga_dw_mmc.c;h=eb69aed9dfb48cfa462489eb3e7fe99664e2d234;hb=8ebde4f0b3e513a41b388893a66ade4a6c292465;hp=bc53a5da272582429a833e79653f2a7632458da7;hpb=8401bfa91ef57e331e2a3abdf768d41803bec88e;p=u-boot

diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index bc53a5da27..eb69aed9df 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <dwmmc.h>
+#include <errno.h>
 #include <asm/arch/dwmmc.h>
 #include <asm/arch/clock_manager.h>
 #include <asm/arch/system_manager.h>
@@ -16,15 +17,13 @@ static const struct socfpga_clock_manager *clock_manager_base =
 static const struct socfpga_system_manager *system_manager_base =
 		(void *)SOCFPGA_SYSMGR_ADDRESS;
 
-static char *SOCFPGA_NAME = "SOCFPGA DWMMC";
-
 static void socfpga_dwmci_clksel(struct dwmci_host *host)
 {
 	unsigned int drvsel;
 	unsigned int smplsel;
 
 	/* Disable SDMMC clock. */
-	clrbits_le32(&clock_manager_base->per_pll_en,
+	clrbits_le32(&clock_manager_base->per_pll.en,
 		CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
 
 	/* Configures drv_sel and smpl_sel */
@@ -39,26 +38,34 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
 		readl(&system_manager_base->sdmmcgrp_ctrl));
 
 	/* Enable SDMMC clock */
-	setbits_le32(&clock_manager_base->per_pll_en,
+	setbits_le32(&clock_manager_base->per_pll.en,
 		CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
 }
 
 int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
 {
-	struct dwmci_host *host = NULL;
-	host = calloc(sizeof(struct dwmci_host), 1);
+	struct dwmci_host *host;
+	unsigned long clk = cm_get_mmc_controller_clk_hz();
+
+	if (clk == 0) {
+		printf("%s: MMC clock is zero!", __func__);
+		return -EINVAL;
+	}
+
+	/* calloc for zero init */
+	host = calloc(1, sizeof(struct dwmci_host));
 	if (!host) {
-		printf("dwmci_host calloc fail!\n");
-		return -1;
+		printf("%s: calloc() failed!\n", __func__);
+		return -ENOMEM;
 	}
 
-	host->name = SOCFPGA_NAME;
+	host->name = "SOCFPGA DWMMC";
 	host->ioaddr = (void *)regbase;
 	host->buswidth = bus_width;
 	host->clksel = socfpga_dwmci_clksel;
 	host->dev_index = index;
 	/* fixed clock divide by 4 which due to the SDMMC wrapper */
-	host->bus_hz = CONFIG_SOCFPGA_DWMMC_BUS_HZ;
+	host->bus_hz = clk;
 	host->fifoth_val = MSIZE(0x2) |
 		RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) |
 		TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2);