X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fmtd%2Fspi%2Fspi_flash.c;h=2911729b289ed077996cf2cf0c1745fe187204f1;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=ab7910bc1450ffe25ef8d541425a98db1296a92d;hpb=576a085c1d224b8a5a3ccf5c4114d07a1f695f20;p=u-boot diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index ab7910bc14..2911729b28 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * SPI Flash Core * @@ -5,8 +6,6 @@ * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik * Copyright (C) 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -16,12 +15,11 @@ #include #include #include +#include #include #include "sf_internal.h" -DECLARE_GLOBAL_DATA_PTR; - static void spi_flash_addr(u32 addr, u8 *cmd) { /* cmd[0] is actual command */ @@ -113,6 +111,27 @@ static int write_cr(struct spi_flash *flash, u8 wc) #endif #ifdef CONFIG_SPI_FLASH_BAR +/* + * This "clean_bar" is necessary in a situation when one was accessing + * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit. + * + * After it the BA24 bit shall be cleared to allow access to correct + * memory region after SW reset (by calling "reset" command). + * + * Otherwise, the BA24 bit may be left set and then after reset, the + * ROM would read/write/erase SPL from 16 MiB * bank_sel address. + */ +static int clean_bar(struct spi_flash *flash) +{ + u8 cmd, bank_sel = 0; + + if (flash->bank_curr == 0) + return 0; + cmd = flash->bank_write_cmd; + + return spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); +} + static int write_bar(struct spi_flash *flash, u32 offset) { u8 cmd, bank_sel; @@ -299,7 +318,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) erase_size = flash->erase_size; if (offset % erase_size || len % erase_size) { - debug("SF: Erase offset/length not multiple of erase size\n"); + printf("SF: Erase offset/length not multiple of erase size\n"); return -1; } @@ -339,6 +358,10 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) len -= erase_size; } +#ifdef CONFIG_SPI_FLASH_BAR + ret = clean_bar(flash); +#endif + return ret; } @@ -380,7 +403,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, if (spi->max_write_size) chunk_len = min(chunk_len, - (size_t)spi->max_write_size); + spi->max_write_size - sizeof(cmd)); spi_flash_addr(write_addr, cmd); @@ -397,6 +420,10 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, offset += chunk_len; } +#ifdef CONFIG_SPI_FLASH_BAR + ret = clean_bar(flash); +#endif + return ret; } @@ -487,6 +514,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, else read_len = remain_len; + if (spi->max_read_size) + read_len = min(read_len, spi->max_read_size); + spi_flash_addr(read_addr, cmd); ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); @@ -500,11 +530,173 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, data += read_len; } +#ifdef CONFIG_SPI_FLASH_BAR + ret = clean_bar(flash); +#endif + free(cmd); return ret; } #ifdef CONFIG_SPI_FLASH_SST +static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl) +{ + switch (ctl) { + case SST26_CTL_LOCK: + cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8); + break; + case SST26_CTL_UNLOCK: + cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8); + break; + case SST26_CTL_CHECK: + return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8)); + } + + return false; +} + +/* + * sst26wf016/sst26wf032/sst26wf064 have next block protection: + * 4x - 8 KByte blocks - read & write protection bits - upper addresses + * 1x - 32 KByte blocks - write protection bits + * rest - 64 KByte blocks - write protection bits + * 1x - 32 KByte blocks - write protection bits + * 4x - 8 KByte blocks - read & write protection bits - lower addresses + * + * We'll support only per 64k lock/unlock so lower and upper 64 KByte region + * will be treated as single block. + */ + +/* + * Lock, unlock or check lock status of the flash region of the flash (depending + * on the lock_ctl value) + */ +static int sst26_lock_ctl(struct spi_flash *flash, u32 ofs, size_t len, enum lock_ctl ctl) +{ + u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size; + bool lower_64k = false, upper_64k = false; + u8 cmd, bpr_buff[SST26_MAX_BPR_REG_LEN] = {}; + int ret; + + /* Check length and offset for 64k alignment */ + if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) + return -EINVAL; + + if (ofs + len > flash->size) + return -EINVAL; + + /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */ + if (flash->size != SZ_2M && + flash->size != SZ_4M && + flash->size != SZ_8M) + return -EINVAL; + + bpr_size = 2 + (flash->size / SZ_64K / 8); + + cmd = SST26_CMD_READ_BPR; + ret = spi_flash_read_common(flash, &cmd, 1, bpr_buff, bpr_size); + if (ret < 0) { + printf("SF: fail to read block-protection register\n"); + return ret; + } + + rptr_64k = min_t(u32, ofs + len , flash->size - SST26_BOUND_REG_SIZE); + lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE); + + upper_64k = ((ofs + len) > (flash->size - SST26_BOUND_REG_SIZE)); + lower_64k = (ofs < SST26_BOUND_REG_SIZE); + + /* Lower bits in block-protection register are about 64k region */ + bpr_ptr = lptr_64k / SZ_64K - 1; + + /* Process 64K blocks region */ + while (lptr_64k < rptr_64k) { + if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) + return EACCES; + + bpr_ptr++; + lptr_64k += SZ_64K; + } + + /* 32K and 8K region bits in BPR are after 64k region bits */ + bpr_ptr = (flash->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K; + + /* Process lower 32K block region */ + if (lower_64k) + if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) + return EACCES; + + bpr_ptr++; + + /* Process upper 32K block region */ + if (upper_64k) + if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) + return EACCES; + + bpr_ptr++; + + /* Process lower 8K block regions */ + for (i = 0; i < SST26_BPR_8K_NUM; i++) { + if (lower_64k) + if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) + return EACCES; + + /* In 8K area BPR has both read and write protection bits */ + bpr_ptr += 2; + } + + /* Process upper 8K block regions */ + for (i = 0; i < SST26_BPR_8K_NUM; i++) { + if (upper_64k) + if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) + return EACCES; + + /* In 8K area BPR has both read and write protection bits */ + bpr_ptr += 2; + } + + /* If we check region status we don't need to write BPR back */ + if (ctl == SST26_CTL_CHECK) + return 0; + + cmd = SST26_CMD_WRITE_BPR; + ret = spi_flash_write_common(flash, &cmd, 1, bpr_buff, bpr_size); + if (ret < 0) { + printf("SF: fail to write block-protection register\n"); + return ret; + } + + return 0; +} + +static int sst26_unlock(struct spi_flash *flash, u32 ofs, size_t len) +{ + return sst26_lock_ctl(flash, ofs, len, SST26_CTL_UNLOCK); +} + +static int sst26_lock(struct spi_flash *flash, u32 ofs, size_t len) +{ + return sst26_lock_ctl(flash, ofs, len, SST26_CTL_LOCK); +} + +/* + * Returns EACCES (positive value) if region is locked, 0 if region is unlocked, + * and negative on errors. + */ +static int sst26_is_locked(struct spi_flash *flash, u32 ofs, size_t len) +{ + /* + * is_locked function is used for check before reading or erasing flash + * region, so offset and length might be not 64k allighned, so adjust + * them to be 64k allighned as sst26_lock_ctl works only with 64k + * allighned regions. + */ + ofs -= ofs & (SZ_64K - 1); + len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len; + + return sst26_lock_ctl(flash, ofs, len, SST26_CTL_CHECK); +} + static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) { struct spi_slave *spi = flash->spi; @@ -914,14 +1106,13 @@ static int set_quad_mode(struct spi_flash *flash, } #if CONFIG_IS_ENABLED(OF_CONTROL) -int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) +int spi_flash_decode_fdt(struct spi_flash *flash) { #ifdef CONFIG_DM_SPI_FLASH fdt_addr_t addr; fdt_size_t size; - int node = dev_of_offset(flash->dev); - addr = fdtdec_get_addr_size(blob, node, "memory-map", &size); + addr = dev_read_addr_size(flash->dev, "memory-map", &size); if (addr == FDT_ADDR_T_NONE) { debug("%s: Cannot decode address\n", __func__); return 0; @@ -948,11 +1139,25 @@ int spi_flash_scan(struct spi_flash *flash) if (IS_ERR_OR_NULL(info)) return -ENOENT; - /* Flash powers up read-only, so clear BP# bits */ + /* + * Flash powers up read-only, so clear BP# bits. + * + * Note on some flash (like Macronix), QE (quad enable) bit is in the + * same status register as BP# bits, and we need preserve its original + * value during a reboot cycle as this is required by some platforms + * (like Intel ICH SPI controller working under descriptor mode). + */ if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) - write_sr(flash, 0); + (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) || + (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX)) { + u8 sr = 0; + + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { + read_sr(flash, &sr); + sr &= STATUS_QEB_MXIC; + } + write_sr(flash, sr); + } flash->name = info->name; flash->memory_map = spi->memory_map; @@ -984,6 +1189,15 @@ int spi_flash_scan(struct spi_flash *flash) } #endif +/* sst26wf series block protection implementation differs from other series */ +#if defined(CONFIG_SPI_FLASH_SST) + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST && info->id[1] == 0x26) { + flash->flash_lock = sst26_lock; + flash->flash_unlock = sst26_unlock; + flash->flash_is_locked = sst26_is_locked; + } +#endif + /* Compute the flash size */ flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; flash->page_size = info->page_size; @@ -1081,7 +1295,7 @@ int spi_flash_scan(struct spi_flash *flash) #endif #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) - ret = spi_flash_decode_fdt(gd->fdt_blob, flash); + ret = spi_flash_decode_fdt(flash); if (ret) { debug("SF: FDT decode error\n"); return -EINVAL;