X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fnet%2Faltera_tse.h;h=2b1af8142978d6526989838d5dd50e85d5f93150;hb=c03411730215dadec9e4c2edcb8119e85bc4a406;hp=0981308a87104c7d1c06defaa0aa27a19d4dbb55;hpb=14fb5369909796f8de1a7fa0c8de1384d3dd2777;p=u-boot

diff --git a/drivers/net/altera_tse.h b/drivers/net/altera_tse.h
index 0981308a87..2b1af81429 100644
--- a/drivers/net/altera_tse.h
+++ b/drivers/net/altera_tse.h
@@ -13,12 +13,16 @@
 
 #define __packed_1_    __packed __aligned(1)
 
+/* dma type */
+#define ALT_SGDMA	0
+#define ALT_MSGDMA	1
+
 /* SGDMA Stuff */
-#define ALT_SGDMA_STATUS_BUSY_MSK			0x00000010
+#define ALT_SGDMA_STATUS_BUSY_MSK				BIT(4)
 
-#define ALT_SGDMA_CONTROL_RUN_MSK			0x00000020
-#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK		0x00000040
-#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK		0x00010000
+#define ALT_SGDMA_CONTROL_RUN_MSK				BIT(5)
+#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK			BIT(6)
+#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK			BIT(16)
 
 /*
  * Descriptor control bit masks & offsets
@@ -27,10 +31,10 @@
  *	 The following bit-offsets are expressed relative to the LSB of
  *	 the control register bitfield.
  */
-#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK		0x00000001
-#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK	0x00000002
-#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK	0x00000004
-#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK		0x00000080
+#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK		BIT(0)
+#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK	BIT(1)
+#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK	BIT(2)
+#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK		BIT(7)
 
 /*
  * Descriptor status bit masks & offsets
@@ -39,7 +43,7 @@
  *	 The following bit-offsets are expressed relative to the LSB of
  *	 the status register bitfield.
  */
-#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK	0x00000080
+#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK	BIT(7)
 
 /*
  * The SGDMA controller buffer descriptor allocates
@@ -84,13 +88,71 @@ struct alt_sgdma_registers {
 	u32 descriptor_pad[3];
 };
 
+/* mSGDMA Stuff */
+
+/* mSGDMA extended descriptor format */
+struct msgdma_extended_desc {
+	u32 read_addr_lo;	/* data buffer source address low bits */
+	u32 write_addr_lo;	/* data buffer destination address low bits */
+	u32 len;
+	u32 burst_seq_num;
+	u32 stride;
+	u32 read_addr_hi;	/* data buffer source address high bits */
+	u32 write_addr_hi;	/* data buffer destination address high bits */
+	u32 control;		/* characteristics of the transfer */
+};
+
+/* mSGDMA descriptor control field bit definitions */
+#define MSGDMA_DESC_CTL_GEN_SOP		BIT(8)
+#define MSGDMA_DESC_CTL_GEN_EOP		BIT(9)
+#define MSGDMA_DESC_CTL_END_ON_EOP	BIT(12)
+#define MSGDMA_DESC_CTL_END_ON_LEN	BIT(13)
+#define MSGDMA_DESC_CTL_GO		BIT(31)
+
+/* Tx buffer control flags */
+#define MSGDMA_DESC_CTL_TX_SINGLE	(MSGDMA_DESC_CTL_GEN_SOP |	\
+					 MSGDMA_DESC_CTL_GEN_EOP |	\
+					 MSGDMA_DESC_CTL_GO)
+
+#define MSGDMA_DESC_CTL_RX_SINGLE	(MSGDMA_DESC_CTL_END_ON_EOP |	\
+					 MSGDMA_DESC_CTL_END_ON_LEN |	\
+					 MSGDMA_DESC_CTL_GO)
+
+/* mSGDMA extended descriptor stride definitions */
+#define MSGDMA_DESC_TX_STRIDE		0x00010001
+#define MSGDMA_DESC_RX_STRIDE		0x00010001
+
+/* mSGDMA dispatcher control and status register map */
+struct msgdma_csr {
+	u32 status;		/* Read/Clear */
+	u32 control;		/* Read/Write */
+	u32 rw_fill_level;
+	u32 resp_fill_level;	/* bit 15:0 */
+	u32 rw_seq_num;
+	u32 pad[3];		/* reserved */
+};
+
+/* mSGDMA CSR status register bit definitions */
+#define MSGDMA_CSR_STAT_BUSY			BIT(0)
+#define MSGDMA_CSR_STAT_RESETTING		BIT(6)
+#define MSGDMA_CSR_STAT_MASK			0x3FF
+
+/* mSGDMA CSR control register bit definitions */
+#define MSGDMA_CSR_CTL_RESET			BIT(1)
+
+/* mSGDMA response register map */
+struct msgdma_response {
+	u32 bytes_transferred;
+	u32 status;
+};
+
 /* TSE Stuff */
-#define ALTERA_TSE_CMD_TX_ENA_MSK		0x00000001
-#define ALTERA_TSE_CMD_RX_ENA_MSK		0x00000002
-#define ALTERA_TSE_CMD_ETH_SPEED_MSK		0x00000008
-#define ALTERA_TSE_CMD_HD_ENA_MSK		0x00000400
-#define ALTERA_TSE_CMD_SW_RESET_MSK		0x00002000
-#define ALTERA_TSE_CMD_ENA_10_MSK		0x02000000
+#define ALTERA_TSE_CMD_TX_ENA_MSK		BIT(0)
+#define ALTERA_TSE_CMD_RX_ENA_MSK		BIT(1)
+#define ALTERA_TSE_CMD_ETH_SPEED_MSK		BIT(3)
+#define ALTERA_TSE_CMD_HD_ENA_MSK		BIT(10)
+#define ALTERA_TSE_CMD_SW_RESET_MSK		BIT(13)
+#define ALTERA_TSE_CMD_ENA_10_MSK		BIT(25)
 
 #define ALT_TSE_SW_RESET_TIMEOUT		(3 * CONFIG_SYS_HZ)
 #define ALT_TSE_SGDMA_BUSY_TIMEOUT		(3 * CONFIG_SYS_HZ)
@@ -141,19 +203,29 @@ struct alt_tse_mac {
 	u32 reserved3[0x38];
 };
 
+struct tse_ops {
+	int (*send)(struct udevice *dev, void *packet, int length);
+	int (*recv)(struct udevice *dev, int flags, uchar **packetp);
+	int (*free_pkt)(struct udevice *dev, uchar *packet, int length);
+	void (*stop)(struct udevice *dev);
+};
+
 struct altera_tse_priv {
 	struct alt_tse_mac *mac_dev;
-	struct alt_sgdma_registers *sgdma_rx;
-	struct alt_sgdma_registers *sgdma_tx;
+	void *sgdma_rx;
+	void *sgdma_tx;
 	unsigned int rx_fifo_depth;
 	unsigned int tx_fifo_depth;
-	struct alt_sgdma_descriptor *rx_desc;
-	struct alt_sgdma_descriptor *tx_desc;
+	void *rx_desc;
+	void *tx_desc;
+	void *rx_resp;
 	unsigned char *rx_buf;
 	unsigned int phyaddr;
 	unsigned int interface;
 	struct phy_device *phydev;
 	struct mii_dev *bus;
+	const struct tse_ops *ops;
+	int dma_type;
 };
 
 #endif /* _ALTERA_TSE_H_ */