X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fnet%2Fbfin_mac.c;h=26a626b4cbd59eea4eef55886213bf6c3d2cde66;hb=154bf12f78c012895e7b42f844b7b92c4f015509;hp=e691bdf2111f4e6f009e7194bb10af99f0c08618;hpb=94060a158f6c67ccd10d90e262e25349bb8cc9dc;p=u-boot diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index e691bdf211..26a626b4cb 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -13,9 +13,11 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -71,18 +73,20 @@ static int bfin_miiphy_wait(void) return 0; } -static int bfin_miiphy_read(char *devname, uchar addr, uchar reg, ushort *val) +static int bfin_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) { + ushort val = 0; if (bfin_miiphy_wait()) return 1; bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY); if (bfin_miiphy_wait()) return 1; - *val = bfin_read_EMAC_STADAT(); - return 0; + val = bfin_read_EMAC_STADAT(); + return val; } -static int bfin_miiphy_write(char *devname, uchar addr, uchar reg, ushort val) +static int bfin_miiphy_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 val) { if (bfin_miiphy_wait()) return 1; @@ -112,31 +116,40 @@ int bfin_EMAC_initialize(bd_t *bis) eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = bfin_miiphy_read; + mdiodev->write = bfin_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; + + dev->priv = mdiodev; #endif return 0; } -static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, - int length) +static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length) { int i; int result = 0; - unsigned int *buf; - buf = (unsigned int *)packet; if (length <= 0) { printf("Ethernet: bad packet size: %d\n", length); goto out; } - if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) { + if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) { printf("Ethernet: tx DMA error\n"); goto out; } - for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) { + for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) { if (i > TOUT_LOOP) { puts("Ethernet: tx time out\n"); goto out; @@ -145,9 +158,9 @@ static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, txbuf[txIdx]->FrmData->NoBytes = length; memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length); txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData; - *pDMA2_NEXT_DESC_PTR = txbuf[txIdx]->Dma; - *pDMA2_CONFIG = txdmacfg.data; - *pEMAC_OPMODE |= TE; + bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma); + bfin_write_DMA2_CONFIG(txdmacfg.data); + bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) { if (i > TOUT_LOOP) { @@ -191,10 +204,9 @@ static int bfin_EMAC_recv(struct eth_device *dev) debug("%s: len = %d\n", __func__, length - 4); - NetRxPackets[rxIdx] = - (volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest); - NetReceive(NetRxPackets[rxIdx], length - 4); - *pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR; + net_rx_packets[rxIdx] = rxbuf[rxIdx]->FrmData->Dest; + net_process_received_packet(net_rx_packets[rxIdx], length - 4); + bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR); rxbuf[rxIdx]->StatusWord = 0x00000000; if ((rxIdx + 1) >= PKTBUFSRX) rxIdx = 0; @@ -225,11 +237,12 @@ static int bfin_EMAC_recv(struct eth_device *dev) static int bfin_miiphy_init(struct eth_device *dev, int *opmode) { const unsigned short pins[] = CONFIG_BFIN_MAC_PINS; - u16 phydat; + int phydat; size_t count; + struct mii_dev *mdiodev = dev->priv; /* Enable PHY output */ - *pVR_CTL |= CLKBUFOE; + bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); /* Set all the pins to peripheral mode */ peripheral_request_list(pins, "bfin_mac"); @@ -239,12 +252,15 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode) bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); /* turn on auto-negotiation and wait for link to come up */ - bfin_miiphy_write(dev->name, CONFIG_PHY_ADDR, MII_BMCR, BMCR_ANENABLE); + bfin_miiphy_write(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE, MII_BMCR, + BMCR_ANENABLE); count = 0; while (1) { ++count; - if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_BMSR, &phydat)) - return -1; + phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR, + MDIO_DEVAD_NONE, MII_BMSR); + if (phydat < 0) + return phydat; if (phydat & BMSR_LSTATUS) break; if (count > 30000) { @@ -255,40 +271,46 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode) } /* see what kind of link we have */ - if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_LPA, &phydat)) - return -1; + phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE, + MII_LPA); + if (phydat < 0) + return phydat; if (phydat & LPA_DUPLEX) *opmode = FDMODE; else *opmode = 0; bfin_write_EMAC_MMC_CTL(RSTC | CROLL); + bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL); + bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL); /* Initialize the TX DMA channel registers */ - *pDMA2_X_COUNT = 0; - *pDMA2_X_MODIFY = 4; - *pDMA2_Y_COUNT = 0; - *pDMA2_Y_MODIFY = 0; + bfin_write_DMA2_X_COUNT(0); + bfin_write_DMA2_X_MODIFY(4); + bfin_write_DMA2_Y_COUNT(0); + bfin_write_DMA2_Y_MODIFY(0); /* Initialize the RX DMA channel registers */ - *pDMA1_X_COUNT = 0; - *pDMA1_X_MODIFY = 4; - *pDMA1_Y_COUNT = 0; - *pDMA1_Y_MODIFY = 0; + bfin_write_DMA1_X_COUNT(0); + bfin_write_DMA1_X_MODIFY(4); + bfin_write_DMA1_Y_COUNT(0); + bfin_write_DMA1_Y_MODIFY(0); return 0; } static int bfin_EMAC_setup_addr(struct eth_device *dev) { - *pEMAC_ADDRLO = + bfin_write_EMAC_ADDRLO( dev->enetaddr[0] | dev->enetaddr[1] << 8 | dev->enetaddr[2] << 16 | - dev->enetaddr[3] << 24; - *pEMAC_ADDRHI = + dev->enetaddr[3] << 24 + ); + bfin_write_EMAC_ADDRHI( dev->enetaddr[4] | - dev->enetaddr[5] << 8; + dev->enetaddr[5] << 8 + ); return 0; } @@ -328,8 +350,8 @@ static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd) } /* Set RX DMA */ - *pDMA1_NEXT_DESC_PTR = rxbuf[0]->Dma; - *pDMA1_CONFIG = rxbuf[0]->Dma[0].CONFIG_DATA; + bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma); + bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA); /* Wait MII done */ bfin_miiphy_wait(); @@ -350,7 +372,7 @@ static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd) opmode |= TE | RMII; #endif /* Turn on the EMAC */ - *pEMAC_OPMODE = opmode; + bfin_write_EMAC_OPMODE(opmode); return 0; } @@ -358,11 +380,10 @@ static void bfin_EMAC_halt(struct eth_device *dev) { debug("Eth_halt: ......\n"); /* Turn off the EMAC */ - *pEMAC_OPMODE = 0x00000000; + bfin_write_EMAC_OPMODE(0); /* Turn off the EMAC RX DMA */ - *pDMA1_CONFIG = 0x0000; - *pDMA2_CONFIG = 0x0000; - + bfin_write_DMA1_CONFIG(0); + bfin_write_DMA2_CONFIG(0); } ADI_ETHER_BUFFER *SetupRxBuffer(int no) @@ -443,16 +464,19 @@ int ether_post_test(int flags) uchar buf[64]; int i, value = 0; int length; + uint addr; printf("\n--------"); bfin_EMAC_init(NULL, NULL); /* construct the package */ - buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF); - buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8); - buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16); - buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24); - buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF); - buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8); + addr = bfin_read_EMAC_ADDRLO(); + buf[0] = buf[6] = addr; + buf[1] = buf[7] = addr >> 8; + buf[2] = buf[8] = addr >> 16; + buf[3] = buf[9] = addr >> 24; + addr = bfin_read_EMAC_ADDRHI(); + buf[4] = buf[10] = addr; + buf[5] = buf[11] = addr >> 8; buf[12] = 0x08; /* Type: ARP */ buf[13] = 0x06; buf[14] = 0x00; /* Hardware type: Ethernet */ @@ -467,7 +491,7 @@ int ether_post_test(int flags) for (i = 0; i < 42; i++) buf[i + 22] = i; printf("--------Send 64 bytes......\n"); - bfin_EMAC_send(NULL, (volatile void *)buf, 64); + bfin_EMAC_send(NULL, buf, 64); for (i = 0; i < 100; i++) { udelay(10000); if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {