X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fnet%2Flpc32xx_eth.c;h=6033392945c12806de358c1345ef63342670b5d5;hb=fe0596cac3079a74eeee93e2940010a7a158c58d;hp=fcadf0c77f22a82736f69ffff63a07fe05d662b5;hpb=c175f306b3f8885965f63ff6c71df5c0f899b4c9;p=u-boot

diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c
index fcadf0c77f..6033392945 100644
--- a/drivers/net/lpc32xx_eth.c
+++ b/drivers/net/lpc32xx_eth.c
@@ -170,7 +170,7 @@ struct lpc32xx_eth_registers {
 #define COMMAND_PASSRUNTFRAME 0x00000040
 #define COMMAND_FULL_DUPLEX   0x00000400
 /* Helper: general reset */
-#define COMMAND_RESETS        0x0000001C
+#define COMMAND_RESETS        0x00000038
 
 /* STATUS register bitfields/masks and offsets (see Table 283) */
 #define STATUS_RXSTATUS 0x00000001
@@ -419,10 +419,12 @@ static int lpc32xx_eth_recv(struct eth_device *dev)
 	rx_index = readl(&regs->rxconsumeindex);
 
 	/* if data was valid, pass it on */
-	if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS))
-		NetReceive(&(bufs->rx_buf[rx_index*PKTSIZE_ALIGN]),
-			   (bufs->rx_stat[rx_index].statusinfo
-			    & RX_STAT_RXSIZE) + 1);
+	if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) {
+		net_process_received_packet(
+			&(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]),
+			(bufs->rx_stat[rx_index].statusinfo
+			 & RX_STAT_RXSIZE) + 1);
+	}
 
 	/* pass receive slot back to DMA engine */
 	rx_index = (rx_index + 1) % RX_BUF_COUNT;
@@ -628,7 +630,7 @@ int lpc32xx_eth_initialize(bd_t *bis)
 	eth_register(dev);
 
 #if defined(CONFIG_PHYLIB)
-	lpc32xx_eth_phylib_init(dev, 0);
+	lpc32xx_eth_phylib_init(dev, CONFIG_PHY_ADDR);
 #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 	miiphy_register(dev->name, mii_reg_read, mii_reg_write);
 #endif