X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fnet%2Fmcffec.c;h=64be5de52facdceb0b09c363994d7f5ea50852a5;hb=f45c07dbd185650c1298399cd5b3a31a29cf0e5a;hp=58ed5e32c6b22a49f2252b04074e93475861ac6b;hpb=cdeb62e20d94005f2e80604fda03b498c3a6f704;p=u-boot diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 58ed5e32c6..64be5de52f 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -27,13 +27,14 @@ #include #include -#include -#include - #include #include +#include #include +#include +#include + #undef ET_DEBUG #undef MII_DEBUG @@ -50,12 +51,12 @@ DECLARE_GLOBAL_DATA_PTR; struct fec_info_s fec_info[] = { -#ifdef CFG_FEC0_IOBASE +#ifdef CONFIG_SYS_FEC0_IOBASE { 0, /* index */ - CFG_FEC0_IOBASE, /* io base */ - CFG_FEC0_PINMUX, /* gpio pin muxing */ - CFG_FEC0_MIIBASE, /* mii base */ + CONFIG_SYS_FEC0_IOBASE, /* io base */ + CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */ + CONFIG_SYS_FEC0_MIIBASE, /* mii base */ -1, /* phy_addr */ 0, /* duplex and speed */ 0, /* phy name */ @@ -66,24 +67,30 @@ struct fec_info_s fec_info[] = { 0, /* tx Index */ 0, /* tx buffer */ 0, /* initialized flag */ + (struct fec_info_s *)-1, }, #endif -#ifdef CFG_FEC1_IOBASE +#ifdef CONFIG_SYS_FEC1_IOBASE { 1, /* index */ - CFG_FEC1_IOBASE, /* io base */ - CFG_FEC1_PINMUX, /* gpio pin muxing */ - CFG_FEC1_MIIBASE, /* mii base */ + CONFIG_SYS_FEC1_IOBASE, /* io base */ + CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */ + CONFIG_SYS_FEC1_MIIBASE, /* mii base */ -1, /* phy_addr */ 0, /* duplex and speed */ 0, /* phy name */ 0, /* phy name init */ +#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM + (cbd_t *)DBUF_LENGTH, /* RX BD */ +#else 0, /* RX BD */ +#endif 0, /* TX BD */ 0, /* rx Index */ 0, /* tx Index */ 0, /* tx buffer */ 0, /* initialized flag */ + (struct fec_info_s *)-1, } #endif }; @@ -94,18 +101,6 @@ int fec_init(struct eth_device *dev, bd_t * bd); void fec_halt(struct eth_device *dev); void fec_reset(struct eth_device *dev); -extern int fecpin_setclear(struct eth_device *dev, int setclear); - -#ifdef CFG_DISCOVER_PHY -extern void __mii_init(void); -extern uint mii_send(uint mii_cmd); -extern int mii_discover_phy(struct eth_device *dev); -extern int mcffec_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -extern int mcffec_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); -#endif - void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) { if ((dup_spd >> 16) == FULL) { @@ -168,16 +163,22 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) /* Activate transmit Buffer Descriptor polling */ fecp->tdar = 0x01000000; /* Descriptor polling active */ - /* FEC fix for MCF5275, FEC unable to initial transmit data packet. +#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM + /* + * FEC unable to initial transmit data packet. * A nop will ensure the descriptor polling active completed. + * CF Internal RAM has shorter cycle access than DRAM. If use + * DRAM as Buffer descriptor and data, a nop is a must. + * Affect only V2 and V3. */ -#ifdef CONFIG_M5275 __asm__ ("nop"); + #endif -#ifdef CFG_UNIFY_CACHE +#ifdef CONFIG_SYS_UNIFY_CACHE icache_invalid(); #endif + j = 0; while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && (j < MCFFEC_TOUT_LOOP)) { @@ -209,7 +210,9 @@ int fec_recv(struct eth_device *dev) int length; for (;;) { -#ifdef CFG_UNIFY_CACHE +#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM +#endif +#ifdef CONFIG_SYS_UNIFY_CACHE icache_invalid(); #endif /* section 16.9.23.2 */ @@ -413,22 +416,22 @@ int fec_init(struct eth_device *dev, bd_t * bd) struct fec_info_s *info = dev->priv; volatile fec_t *fecp = (fec_t *) (info->iobase); int i; - u8 *ea = NULL; + uchar ea[6]; fecpin_setclear(dev, 1); fec_reset(dev); #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ - defined (CFG_DISCOVER_PHY) + defined (CONFIG_SYS_DISCOVER_PHY) mii_init(); setFecDuplexSpeed(fecp, bd, info->dup_spd); #else -#ifndef CFG_DISCOVER_PHY +#ifndef CONFIG_SYS_DISCOVER_PHY setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); -#endif /* ifndef CFG_DISCOVER_PHY */ +#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */ #endif /* CONFIG_CMD_MII || CONFIG_MII */ /* We use strictly polling mode only */ @@ -438,28 +441,28 @@ int fec_init(struct eth_device *dev, bd_t * bd) fecp->eir = 0xffffffff; /* Set station address */ - if ((u32) fecp == CFG_FEC0_IOBASE) { -#ifdef CFG_FEC1_IOBASE - volatile fec_t *fecp1 = (fec_t *) (CFG_FEC1_IOBASE); - ea = &bd->bi_enet1addr[0]; + if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) { +#ifdef CONFIG_SYS_FEC1_IOBASE + volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE); + eth_getenv_enetaddr("eth1addr", ea); fecp1->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); fecp1->paur = (ea[4] << 24) | (ea[5] << 16); #endif - ea = &bd->bi_enetaddr[0]; + eth_getenv_enetaddr("ethaddr", ea); fecp->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); fecp->paur = (ea[4] << 24) | (ea[5] << 16); } else { -#ifdef CFG_FEC0_IOBASE - volatile fec_t *fecp0 = (fec_t *) (CFG_FEC0_IOBASE); - ea = &bd->bi_enetaddr[0]; +#ifdef CONFIG_SYS_FEC0_IOBASE + volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE); + eth_getenv_enetaddr("ethaddr", ea); fecp0->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); fecp0->paur = (ea[4] << 24) | (ea[5] << 16); #endif -#ifdef CFG_FEC1_IOBASE - ea = &bd->bi_enet1addr[0]; +#ifdef CONFIG_SYS_FEC1_IOBASE + eth_getenv_enetaddr("eth1addr", ea); fecp->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); fecp->paur = (ea[4] << 24) | (ea[5] << 16); @@ -553,11 +556,14 @@ int mcffec_initialize(bd_t * bis) { struct eth_device *dev; int i; +#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM + u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; +#endif for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { dev = - (struct eth_device *)memalign(CFG_CACHELINE_SIZE, + (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof *dev); if (dev == NULL) hang(); @@ -573,20 +579,34 @@ int mcffec_initialize(bd_t * bis) dev->recv = fec_recv; /* setup Receive and Transmit buffer descriptor */ +#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM + fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp); + tmp = (u32)fec_info[i].rxbd; + fec_info[i].txbd = + (cbd_t *)((u32)fec_info[i].txbd + tmp + + (PKTBUFSRX * sizeof(cbd_t))); + tmp = (u32)fec_info[i].txbd; + fec_info[i].txbuf = + (char *)((u32)fec_info[i].txbuf + tmp + + (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); + tmp = (u32)fec_info[i].txbuf; +#else fec_info[i].rxbd = - (cbd_t *) memalign(CFG_CACHELINE_SIZE, + (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, (PKTBUFSRX * sizeof(cbd_t))); fec_info[i].txbd = - (cbd_t *) memalign(CFG_CACHELINE_SIZE, + (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, (TX_BUF_CNT * sizeof(cbd_t))); fec_info[i].txbuf = - (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH); + (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); +#endif + #ifdef ET_DEBUG printf("rxbd %x txbd %x\n", (int)fec_info[i].rxbd, (int)fec_info[i].txbd); #endif - fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32); + fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); eth_register(dev); @@ -594,10 +614,13 @@ int mcffec_initialize(bd_t * bis) miiphy_register(dev->name, mcffec_miiphy_read, mcffec_miiphy_write); #endif + if (i > 0) + fec_info[i - 1].next = &fec_info[i]; } + fec_info[i - 1].next = &fec_info[0]; /* default speed */ bis->bi_ethspeed = 10; - return 1; + return 0; }