X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fnet%2Fmcffec.c;h=fd7309937104407935fada5839769bbcb7eb8381;hb=42800ffa7997082e2466c772bc2395dff0c95e3a;hp=18240a81a4e7e98e885302df084f47e7dcdcf6b8;hpb=e0b0ec843085f96f4fe0738424835ee90e58bc00;p=u-boot diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 18240a81a4..fd73099371 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -5,23 +5,7 @@ * (C) Copyright 2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -95,7 +79,6 @@ struct fec_info_s fec_info[] = { #endif }; -int fec_send(struct eth_device *dev, volatile void *packet, int length); int fec_recv(struct eth_device *dev); int fec_init(struct eth_device *dev, bd_t * bd); void fec_halt(struct eth_device *dev); @@ -134,14 +117,14 @@ void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) } } -int fec_send(struct eth_device *dev, volatile void *packet, int length) +static int fec_send(struct eth_device *dev, void *packet, int length) { struct fec_info_s *info = dev->priv; volatile fec_t *fecp = (fec_t *) (info->iobase); int j, rc; u16 phyStatus; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); + miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus); /* section 16.9.23.3 * Wait for ready @@ -236,7 +219,8 @@ int fec_recv(struct eth_device *dev) length -= 4; /* Pass the packet up to the protocol layers. */ - NetReceive(NetRxPackets[info->rxIdx], length); + net_process_received_packet(net_rx_packets[info->rxIdx], + length); fecp->eir |= FEC_EIR_RXF; } @@ -416,7 +400,7 @@ int fec_init(struct eth_device *dev, bd_t * bd) struct fec_info_s *info = dev->priv; volatile fec_t *fecp = (fec_t *) (info->iobase); int i; - u8 *ea = NULL; + uchar ea[6]; fecpin_setclear(dev, 1); @@ -444,25 +428,25 @@ int fec_init(struct eth_device *dev, bd_t * bd) if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) { #ifdef CONFIG_SYS_FEC1_IOBASE volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE); - ea = &bd->bi_enet1addr[0]; + eth_getenv_enetaddr("eth1addr", ea); fecp1->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); fecp1->paur = (ea[4] << 24) | (ea[5] << 16); #endif - ea = &bd->bi_enetaddr[0]; + eth_getenv_enetaddr("ethaddr", ea); fecp->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); fecp->paur = (ea[4] << 24) | (ea[5] << 16); } else { #ifdef CONFIG_SYS_FEC0_IOBASE volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE); - ea = &bd->bi_enetaddr[0]; + eth_getenv_enetaddr("ethaddr", ea); fecp0->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); fecp0->paur = (ea[4] << 24) | (ea[5] << 16); #endif #ifdef CONFIG_SYS_FEC1_IOBASE - ea = &bd->bi_enet1addr[0]; + eth_getenv_enetaddr("eth1addr", ea); fecp->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); fecp->paur = (ea[4] << 24) | (ea[5] << 16); @@ -494,7 +478,7 @@ int fec_init(struct eth_device *dev, bd_t * bd) for (i = 0; i < PKTBUFSRX; i++) { info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; info->rxbd[i].cbd_datlen = 0; /* Reset */ - info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; + info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; } info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; @@ -560,7 +544,7 @@ int mcffec_initialize(bd_t * bis) u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; #endif - for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { + for (i = 0; i < ARRAY_SIZE(fec_info); i++) { dev = (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,