X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fnet%2Fmpc5xxx_fec.c;h=d75e858a3826d6fc6416cacb0625758fc409e1d5;hb=7f874e2b85a1bbc0a98c538135ad8c658b1856e1;hp=2bf901e138bec5faf46cd9c79111b5605e819a22;hpb=86321fc1128c93a10ac4afb9d317b0df8ece0f9e;p=u-boot diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c index 2bf901e138..d75e858a38 100644 --- a/drivers/net/mpc5xxx_fec.c +++ b/drivers/net/mpc5xxx_fec.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2003-2005 + * (C) Copyright 2003-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * This file is based on mpc4200fec.c, @@ -28,10 +28,6 @@ static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec); static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec); #endif /* DEBUG */ -#if (DEBUG & 0x40) -static uint32 local_crc32(char *string, unsigned int crc_value, int len); -#endif - typedef struct { uint8 data[1500]; /* actual data */ int length; /* actual length */ @@ -39,8 +35,12 @@ typedef struct { uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */ } NBUF; -int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal); -int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data); +int fec5xxx_miiphy_read(struct mii_dev *bus, int phyAddr, int devad, + int regAddr); +int fec5xxx_miiphy_write(struct mii_dev *bus, int phyAddr, int devad, + int regAddr, u16 data); + +static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis); /********************************************************************/ #if (DEBUG & 0x2) @@ -249,6 +249,15 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) printf ("mpc5xxx_fec_init... Begin\n"); #endif + mpc5xxx_fec_init_phy(dev, bis); + + /* + * Call board-specific PHY fixups (if any) + */ +#ifdef CONFIG_RESET_PHY_R + reset_phy(); +#endif + /* * Initialize RxBD/TxBD rings */ @@ -281,13 +290,6 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) } fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */ - if (fec->xcv_type != SEVENWIRE) { - /* - * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock - * and do not drop the Preamble. - */ - fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */ - } /* * Set Opcode/Pause Duration Register @@ -339,13 +341,11 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) */ fec->eth->xmit_fsm = 0x03000000; -#if defined(CONFIG_MPC5200) /* - * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't + * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't * work w/ the current receive task. */ sdma->PtdCntrl |= 0x00000001; -#endif /* * Set priority of different initiators @@ -394,6 +394,11 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) { mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */ + static int initialized = 0; + + if(initialized) + return 0; + initialized = 1; #if (DEBUG & 0x1) printf ("mpc5xxx_fec_init_phy... Begin\n"); @@ -404,13 +409,8 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) */ if (fec->xcv_type == SEVENWIRE) { /* 10MBit with 7-wire operation */ -#if defined(CONFIG_TOTAL5200) - /* 7-wire and USB2 on Ethernet */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000; -#else /* !CONFIG_TOTAL5200 */ /* 7-wire only */ *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000; -#endif /* CONFIG_TOTAL5200 */ } else { /* 100MBit with MD operation */ *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000; @@ -437,8 +437,9 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) /* * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock * and do not drop the Preamble. + * No MII for 7-wire mode */ - fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */ + fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1); } if (fec->xcv_type != SEVENWIRE) { @@ -472,11 +473,6 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) miiphy_write(dev->name, phyAddr, 0x0, 0x8000); udelay(1000); -#if defined(CONFIG_UC101) || defined(CONFIG_MUCMC52) - /* Set the LED configuration Register for the UC101 - and MUCMC52 Board */ - miiphy_write(dev->name, phyAddr, 0x14, 0x4122); -#endif if (fec->xcv_type == MII10) { /* * Force 10Base-T, FDX operation @@ -577,9 +573,7 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) /********************************************************************/ static void mpc5xxx_fec_halt(struct eth_device *dev) { -#if defined(CONFIG_MPC5200) struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; -#endif mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; int counter = 0xffff; @@ -609,13 +603,11 @@ static void mpc5xxx_fec_halt(struct eth_device *dev) SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO); SDMA_TASK_DISABLE (FEC_RECV_TASK_NO); -#if defined(CONFIG_MPC5200) /* - * Turn on COMM bus prefetch in the MGT5200 BestComm after we're + * Turn on COMM bus prefetch in the MPC5200 BestComm after we're * done. It doesn't work w/ the current receive task. */ sdma->PtdCntrl &= ~0x00000001; -#endif /* * Disable the Ethernet Controller @@ -640,6 +632,16 @@ static void mpc5xxx_fec_halt(struct eth_device *dev) */ udelay(10); + /* don't leave the MII speed set to zero */ + if (fec->xcv_type != SEVENWIRE) { + /* + * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock + * and do not drop the Preamble. + * No MII for 7-wire mode + */ + fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1); + } + #if (DEBUG & 0x3) printf("Ethernet task stopped\n"); #endif @@ -699,7 +701,7 @@ static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec) /********************************************************************/ -static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data, +static int mpc5xxx_fec_send(struct eth_device *dev, void *eth_data, int data_length) { /* @@ -859,7 +861,7 @@ static int mpc5xxx_fec_recv(struct eth_device *dev) */ memcpy(buff, frame->head, 14); memcpy(buff + 14, frame->data, frame_length); - NetReceive(buff, frame_length); + net_process_received_packet(buff, frame_length); len = frame_length; } /* @@ -897,6 +899,14 @@ int mpc5xxx_fec_initialize(bd_t * bis) #else #error fec->xcv_type not initialized. #endif + if (fec->xcv_type != SEVENWIRE) { + /* + * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock + * and do not drop the Preamble. + * No MII for 7-wire mode + */ + fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1); + } dev->priv = (void *)fec; dev->iobase = MPC5XXX_FEC; @@ -905,12 +915,21 @@ int mpc5xxx_fec_initialize(bd_t * bis) dev->send = mpc5xxx_fec_send; dev->recv = mpc5xxx_fec_recv; - sprintf(dev->name, "FEC ETHERNET"); + strcpy(dev->name, "FEC"); eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register (dev->name, - fec5xxx_miiphy_read, fec5xxx_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = fec5xxx_miiphy_read; + mdiodev->write = fec5xxx_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif /* @@ -928,15 +947,15 @@ int mpc5xxx_fec_initialize(bd_t * bis) mpc5xxx_fec_set_hwaddr(fec, env_enetaddr); } - mpc5xxx_fec_init_phy(dev, bis); - return 1; } /* MII-interface related functions */ /********************************************************************/ -int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal) +int fec5xxx_miiphy_read(struct mii_dev *bus, int phyAddr, int devad, + int regAddr) { + uint16 retVal = 0; ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC; uint32 reg; /* convenient holder for the PHY register */ uint32 phy; /* convenient holder for the PHY */ @@ -971,13 +990,14 @@ int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * re /* * it's now safe to read the PHY's register */ - *retVal = (uint16) eth->mii_data; + retVal = (uint16) eth->mii_data; - return 0; + return retVal; } /********************************************************************/ -int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data) +int fec5xxx_miiphy_write(struct mii_dev *bus, int phyAddr, int devad, + int regAddr, u16 data) { ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC; uint32 reg; /* convenient holder for the PHY register */ @@ -1009,38 +1029,3 @@ int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 dat return 0; } - -#if (DEBUG & 0x40) -static uint32 local_crc32(char *string, unsigned int crc_value, int len) -{ - int i; - char c; - unsigned int crc, count; - - /* - * crc32 algorithm - */ - /* - * crc = 0xffffffff; * The initialized value should be 0xffffffff - */ - crc = crc_value; - - for (i = len; --i >= 0;) { - c = *string++; - for (count = 0; count < 8; count++) { - if ((c & 0x01) ^ (crc & 0x01)) { - crc >>= 1; - crc = crc ^ 0xedb88320; - } else { - crc >>= 1; - } - c >>= 1; - } - } - - /* - * In big endian system, do byte swaping for crc value - */ - /**/ return crc; -} -#endif /* DEBUG */