X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fnet%2Fns8382x.c;h=45402cc0ec3d7ed8ed79f1c88d058ff22ebfe49a;hb=11e238d6e672ac8b81cabbc7921b0da5554efc3a;hp=f8b143a01a60f25282440776c0c138d21fc4cb16;hpb=4985ca5af3767ffe13ea96e1dc26f88c81084414;p=u-boot

diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c
index f8b143a01a..45402cc0ec 100644
--- a/drivers/net/ns8382x.c
+++ b/drivers/net/ns8382x.c
@@ -42,23 +42,21 @@
 /* Revision History
  * October 2002 mar	1.0
  *   Initial U-Boot Release.
- *   	Tested with Netgear GA622T (83820)
- *   	and SMC9452TX (83821)
- *   	NOTE: custom boards with these chips may (likely) require
- *   	a programmed EEPROM device (if present) in order to work
- *   	correctly.
+ *	Tested with Netgear GA622T (83820)
+ *	and SMC9452TX (83821)
+ *	NOTE: custom boards with these chips may (likely) require
+ *	a programmed EEPROM device (if present) in order to work
+ *	correctly.
 */
 
 /* Includes */
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include <pci.h>
 
-#if defined(CONFIG_CMD_NET) \
-	&& defined(CONFIG_NET_MULTI) && defined(CONFIG_NS8382X)
-
 /* defines */
 #define DSIZE     0x00000FFF
 #define ETH_ALEN		6
@@ -115,50 +113,50 @@ enum ChipConfigBits {
 #define SpeedStatus_Polarity ( GigSpeed | HundSpeed | FullDuplex)
 
 enum TxConfig_bits {
-	TxDrthMask 	= 0x000000ff,
-	TxFlthMask 	= 0x0000ff00,
+	TxDrthMask	= 0x000000ff,
+	TxFlthMask	= 0x0000ff00,
 	TxMxdmaMask	= 0x00700000,
-	TxMxdma_8 	= 0x00100000,
-	TxMxdma_16 	= 0x00200000,
-	TxMxdma_32 	= 0x00300000,
-	TxMxdma_64 	= 0x00400000,
-	TxMxdma_128 	= 0x00500000,
-	TxMxdma_256 	= 0x00600000,
-	TxMxdma_512 	= 0x00700000,
-	TxMxdma_1024 	= 0x00000000,
-	TxCollRetry 	= 0x00800000,
-	TxAutoPad 	= 0x10000000,
-	TxMacLoop 	= 0x20000000,
-	TxHeartIgn 	= 0x40000000,
-	TxCarrierIgn 	= 0x80000000
+	TxMxdma_8	= 0x00100000,
+	TxMxdma_16	= 0x00200000,
+	TxMxdma_32	= 0x00300000,
+	TxMxdma_64	= 0x00400000,
+	TxMxdma_128	= 0x00500000,
+	TxMxdma_256	= 0x00600000,
+	TxMxdma_512	= 0x00700000,
+	TxMxdma_1024	= 0x00000000,
+	TxCollRetry	= 0x00800000,
+	TxAutoPad	= 0x10000000,
+	TxMacLoop	= 0x20000000,
+	TxHeartIgn	= 0x40000000,
+	TxCarrierIgn	= 0x80000000
 };
 
 enum RxConfig_bits {
-	RxDrthMask 	= 0x0000003e,
-	RxMxdmaMask 	= 0x00700000,
-	RxMxdma_8 	= 0x00100000,
-	RxMxdma_16 	= 0x00200000,
-	RxMxdma_32 	= 0x00300000,
-	RxMxdma_64 	= 0x00400000,
-	RxMxdma_128 	= 0x00500000,
-	RxMxdma_256 	= 0x00600000,
-	RxMxdma_512 	= 0x00700000,
-	RxMxdma_1024 	= 0x00000000,
-	RxAcceptLenErr 	= 0x04000000,
-	RxAcceptLong 	= 0x08000000,
-	RxAcceptTx 	= 0x10000000,
-	RxStripCRC 	= 0x20000000,
-	RxAcceptRunt 	= 0x40000000,
-	RxAcceptErr 	= 0x80000000,
+	RxDrthMask	= 0x0000003e,
+	RxMxdmaMask	= 0x00700000,
+	RxMxdma_8	= 0x00100000,
+	RxMxdma_16	= 0x00200000,
+	RxMxdma_32	= 0x00300000,
+	RxMxdma_64	= 0x00400000,
+	RxMxdma_128	= 0x00500000,
+	RxMxdma_256	= 0x00600000,
+	RxMxdma_512	= 0x00700000,
+	RxMxdma_1024	= 0x00000000,
+	RxAcceptLenErr	= 0x04000000,
+	RxAcceptLong	= 0x08000000,
+	RxAcceptTx	= 0x10000000,
+	RxStripCRC	= 0x20000000,
+	RxAcceptRunt	= 0x40000000,
+	RxAcceptErr	= 0x80000000,
 };
 
 /* Bits in the RxMode register. */
 enum rx_mode_bits {
-	RxFilterEnable 		= 0x80000000,
-	AcceptAllBroadcast 	= 0x40000000,
-	AcceptAllMulticast 	= 0x20000000,
-	AcceptAllUnicast 	= 0x10000000,
-	AcceptPerfectMatch 	= 0x08000000,
+	RxFilterEnable		= 0x80000000,
+	AcceptAllBroadcast	= 0x40000000,
+	AcceptAllMulticast	= 0x20000000,
+	AcceptAllUnicast	= 0x10000000,
+	AcceptPerfectMatch	= 0x08000000,
 };
 
 typedef struct _BufferDesc {
@@ -342,6 +340,11 @@ ns8382x_initialize(bd_t * bis)
 		}
 
 		dev = (struct eth_device *) malloc(sizeof *dev);
+		if (!dev) {
+			printf("ns8382x: Can not allocate memory\n");
+			break;
+		}
+		memset(dev, 0, sizeof(*dev));
 
 		sprintf(dev->name, "dp8382x#%d", card_number);
 		dev->iobase = bus_to_phys(iobase);
@@ -447,7 +450,7 @@ ns8382x_initialize(bd_t * bis)
 	Read and write MII registers using software-generated serial MDIO
 	protocol.  See the MII specifications or DP83840A data sheet for details.
 
-	The maximum data clock rate is 2.5 Mhz.  To meet minimum timing we
+	The maximum data clock rate is 2.5 MHz.  To meet minimum timing we
 	must flush writes to the PCI bus with a PCI read. */
 #define mdio_delay(mdio_addr) INL(dev, mdio_addr)
 
@@ -527,7 +530,7 @@ mdio_write(struct eth_device *dev, int phy_id, int addr, int value)
  * Description: resets the ethernet controller chip and configures
  *    registers and data structures required for sending and receiving packets.
  * Arguments: struct eth_device *dev:       NIC data structure
- * returns:  	int.
+ * returns:	int.
  */
 
 static int
@@ -773,14 +776,14 @@ ns8382x_send(struct eth_device *dev, volatile void *packet, int length)
 
 	for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) {
 		if (i >= TOUT_LOOP) {
-			printf ("%s: tx error buffer not ready: txd.cmdsts %#X\n",
+			printf ("%s: tx error buffer not ready: txd.cmdsts %#lX\n",
 			     dev->name, tx_stat);
 			goto Done;
 		}
 	}
 
 	if (!(tx_stat & DescPktOK)) {
-		printf("ns8382x_send: Transmit error, Tx status %X.\n", tx_stat);
+		printf("ns8382x_send: Transmit error, Tx status %lX.\n", tx_stat);
 		goto Done;
 	}
 #ifdef NS8382X_DEBUG
@@ -859,5 +862,3 @@ ns8382x_disable(struct eth_device *dev)
 	/* Restore PME enable bit */
 	OUTL(dev, SavedClkRun, ClkRun);
 }
-
-#endif