X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fnet%2Fns8382x.c;h=45402cc0ec3d7ed8ed79f1c88d058ff22ebfe49a;hb=b9d77535e9335b554af03aa0e0a54b664677d018;hp=c807dd4c7b85851e5c216643ae56c6b75a5d40d3;hpb=53677ef18e25c97ac613349087c5cb33ae5a2741;p=u-boot diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c index c807dd4c7b..45402cc0ec 100644 --- a/drivers/net/ns8382x.c +++ b/drivers/net/ns8382x.c @@ -53,12 +53,10 @@ #include #include #include +#include #include #include -#if defined(CONFIG_CMD_NET) \ - && defined(CONFIG_NET_MULTI) && defined(CONFIG_NS8382X) - /* defines */ #define DSIZE 0x00000FFF #define ETH_ALEN 6 @@ -342,6 +340,11 @@ ns8382x_initialize(bd_t * bis) } dev = (struct eth_device *) malloc(sizeof *dev); + if (!dev) { + printf("ns8382x: Can not allocate memory\n"); + break; + } + memset(dev, 0, sizeof(*dev)); sprintf(dev->name, "dp8382x#%d", card_number); dev->iobase = bus_to_phys(iobase); @@ -447,7 +450,7 @@ ns8382x_initialize(bd_t * bis) Read and write MII registers using software-generated serial MDIO protocol. See the MII specifications or DP83840A data sheet for details. - The maximum data clock rate is 2.5 Mhz. To meet minimum timing we + The maximum data clock rate is 2.5 MHz. To meet minimum timing we must flush writes to the PCI bus with a PCI read. */ #define mdio_delay(mdio_addr) INL(dev, mdio_addr) @@ -773,14 +776,14 @@ ns8382x_send(struct eth_device *dev, volatile void *packet, int length) for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) { if (i >= TOUT_LOOP) { - printf ("%s: tx error buffer not ready: txd.cmdsts %#X\n", + printf ("%s: tx error buffer not ready: txd.cmdsts %#lX\n", dev->name, tx_stat); goto Done; } } if (!(tx_stat & DescPktOK)) { - printf("ns8382x_send: Transmit error, Tx status %X.\n", tx_stat); + printf("ns8382x_send: Transmit error, Tx status %lX.\n", tx_stat); goto Done; } #ifdef NS8382X_DEBUG @@ -859,5 +862,3 @@ ns8382x_disable(struct eth_device *dev) /* Restore PME enable bit */ OUTL(dev, SavedClkRun, ClkRun); } - -#endif