X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fnet%2Fsh_eth.c;h=a7c265b980a8da54743d740d9c386e8fa05a4a73;hb=008ed16c820a4121d34a856c41d143a86eb9e13e;hp=ebe858894c275e17363342e08ddc7aa45bf79ef2;hpb=ee924e00300bd1136589b2d5f8ad1f008df01bd4;p=u-boot diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index ebe858894c..a7c265b980 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -1,23 +1,12 @@ /* - * sh_eth.c - Driver for Renesas SH7763's ethernet controler. + * sh_eth.c - Driver for Renesas ethernet controller. * - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (c) 2008 Nobuhiro Iwamatsu + * Copyright (C) 2008, 2011 Renesas Solutions Corp. + * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu * Copyright (c) 2007 Carlos Munoz + * Copyright (C) 2013, 2014 Renesas Electronics Corporation * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -25,7 +14,8 @@ #include #include #include -#include +#include +#include #include #include "sh_eth.h" @@ -37,147 +27,33 @@ # error "Please define CONFIG_SH_ETHER_PHY_ADDR" #endif -#define SH_ETH_PHY_DELAY 50000 - -/* - * Bits are written to the PHY serially using the - * PIR register, just like a bit banger. - */ -static void sh_eth_mii_write_phy_bits(int port, u32 val, int len) -{ - int i; - u32 pir; - - /* Bit positions is 1 less than the number of bits */ - for (i = len - 1; i >= 0; i--) { - /* Write direction, bit to write, clock is low */ - pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); - outl(pir, PIR(port)); - udelay(1); - /* Write direction, bit to write, clock is high */ - pir = 3 | ((val & 1 << i) ? 1 << 2 : 0); - outl(pir, PIR(port)); - udelay(1); - /* Write direction, bit to write, clock is low */ - pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); - outl(pir, PIR(port)); - udelay(1); - } -} - -static void sh_eth_mii_bus_release(int port) -{ - /* Read direction, clock is low */ - outl(0, PIR(port)); - udelay(1); - /* Read direction, clock is high */ - outl(1, PIR(port)); - udelay(1); - /* Read direction, clock is low */ - outl(0, PIR(port)); - udelay(1); -} - -static void sh_eth_mii_ind_bus_release(int port) -{ - /* Read direction, clock is low */ - outl(0, PIR(port)); - udelay(1); -} +#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF) +#define flush_cache_wback(addr, len) \ + flush_dcache_range((u32)addr, (u32)(addr + len - 1)) +#else +#define flush_cache_wback(...) +#endif -static void sh_eth_mii_read_phy_bits(int port, u32 *val, int len) -{ - int i; - u32 pir; - - *val = 0; - for (i = len - 1; i >= 0; i--) { - /* Read direction, clock is high */ - outl(1, PIR(port)); - udelay(1); - /* Read bit */ - pir = inl(PIR(port)); - *val |= (pir & 8) ? 1 << i : 0; - /* Read direction, clock is low */ - outl(0, PIR(port)); - udelay(1); +#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) +#define invalidate_cache(addr, len) \ + { \ + u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \ + u32 start, end; \ + \ + start = (u32)addr; \ + end = start + len; \ + start &= ~(line_size - 1); \ + end = ((end + line_size - 1) & ~(line_size - 1)); \ + \ + invalidate_dcache_range(start, end); \ } -} - -#define PHY_INIT 0xFFFFFFFF -#define PHY_READ 0x02 -#define PHY_WRITE 0x01 -/* - * To read a phy register, mii managements frames are sent to the phy. - * The frames look like this: - * pre (32 bits): 0xffff ffff - * st (2 bits): 01 - * op (2bits): 10: read 01: write - * phyad (5 bits): xxxxx - * regad (5 bits): xxxxx - * ta (Bus release): - * data (16 bits): read data - */ -static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg) -{ - u32 val; - - /* Sent mii management frame */ - /* pre */ - sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); - /* st (start of frame) */ - sh_eth_mii_write_phy_bits(port, 0x1, 2); - /* op (code) */ - sh_eth_mii_write_phy_bits(port, PHY_READ, 2); - /* phy address */ - sh_eth_mii_write_phy_bits(port, phy_addr, 5); - /* Register to read */ - sh_eth_mii_write_phy_bits(port, reg, 5); - - /* Bus release */ - sh_eth_mii_bus_release(port); - - /* Read register */ - sh_eth_mii_read_phy_bits(port, &val, 16); - - return val; -} +#else +#define invalidate_cache(...) +#endif -/* - * To write a phy register, mii managements frames are sent to the phy. - * The frames look like this: - * pre (32 bits): 0xffff ffff - * st (2 bits): 01 - * op (2bits): 10: read 01: write - * phyad (5 bits): xxxxx - * regad (5 bits): xxxxx - * ta (2 bits): 10 - * data (16 bits): write data - * idle (Independent bus release) - */ -static void sh_eth_mii_write_phy_reg(int port, u8 phy_addr, int reg, u16 val) -{ - /* Sent mii management frame */ - /* pre */ - sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); - /* st (start of frame) */ - sh_eth_mii_write_phy_bits(port, 0x1, 2); - /* op (code) */ - sh_eth_mii_write_phy_bits(port, PHY_WRITE, 2); - /* phy address */ - sh_eth_mii_write_phy_bits(port, phy_addr, 5); - /* Register to read */ - sh_eth_mii_write_phy_bits(port, reg, 5); - /* ta */ - sh_eth_mii_write_phy_bits(port, PHY_READ, 2); - /* Write register data */ - sh_eth_mii_write_phy_bits(port, val, 16); - - /* Independent bus release */ - sh_eth_mii_ind_bus_release(port); -} +#define TIMEOUT_CNT 1000 -int sh_eth_send(struct eth_device *dev, volatile void *packet, int len) +int sh_eth_send(struct eth_device *dev, void *packet, int len) { struct sh_eth_dev *eth = dev->priv; int port = eth->port, ret = 0, timeout; @@ -190,13 +66,15 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len) } /* packet must be a 4 byte boundary */ - if ((int)packet & (4 - 1)) { - printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__); + if ((int)packet & 3) { + printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n" + , __func__); ret = -EFAULT; goto err; } /* Update tx descriptor */ + flush_cache_wback(packet, len); port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); port_info->tx_desc_cur->td1 = len << 16; /* Must preserve the end of descriptor list indication */ @@ -205,14 +83,19 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len) else port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; + flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s)); + /* Restart the transmitter if disabled */ - if (!(inl(EDTRR(port)) & EDTRR_TRNS)) - outl(EDTRR_TRNS, EDTRR(port)); + if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS)) + sh_eth_write(eth, EDTRR_TRNS, EDTRR); /* Wait until packet is transmitted */ - timeout = 1000; - while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--) + timeout = TIMEOUT_CNT; + do { + invalidate_cache(port_info->tx_desc_cur, + sizeof(struct tx_desc_s)); udelay(100); + } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--); if (timeout < 0) { printf(SHETHER_NAME ": transmit timeout\n"); @@ -224,7 +107,6 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len) if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) port_info->tx_desc_cur = port_info->tx_desc_base; - return ret; err: return ret; } @@ -234,16 +116,18 @@ int sh_eth_recv(struct eth_device *dev) struct sh_eth_dev *eth = dev->priv; int port = eth->port, len = 0; struct sh_eth_info *port_info = ð->port_info[port]; - volatile u8 *packet; + uchar *packet; /* Check if the rx descriptor is ready */ + invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s)); if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { /* Check for errors */ if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { len = port_info->rx_desc_cur->rd1 & 0xffff; - packet = (volatile u8 *) - ADDR_TO_P2(port_info->rx_desc_cur->rd2); - NetReceive(packet, len); + packet = (uchar *) + ADDR_TO_P2(port_info->rx_desc_cur->rd2); + invalidate_cache(packet, len); + net_process_received_packet(packet, len); } /* Make current descriptor available again */ @@ -252,6 +136,9 @@ int sh_eth_recv(struct eth_device *dev) else port_info->rx_desc_cur->rd0 = RD_RACT; + flush_cache_wback(port_info->rx_desc_cur, + sizeof(struct rx_desc_s)); + /* Point to the next descriptor */ port_info->rx_desc_cur++; if (port_info->rx_desc_cur >= @@ -260,60 +147,67 @@ int sh_eth_recv(struct eth_device *dev) } /* Restart the receiver if disabled */ - if (!(inl(EDRRR(port)) & EDRRR_R)) - outl(EDRRR_R, EDRRR(port)); + if (!(sh_eth_read(eth, EDRRR) & EDRRR_R)) + sh_eth_write(eth, EDRRR_R, EDRRR); return len; } -#define EDMR_INIT_CNT 1000 static int sh_eth_reset(struct sh_eth_dev *eth) { - int port = eth->port; +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) int ret = 0, i; /* Start e-dmac transmitter and receiver */ - outl(EDSR_ENALL, EDSR(port)); + sh_eth_write(eth, EDSR_ENALL, EDSR); /* Perform a software reset and wait for it to complete */ - outl(EDMR_SRST, EDMR(port)); - for (i = 0; i < EDMR_INIT_CNT; i++) { - if (!(inl(EDMR(port)) & EDMR_SRST)) + sh_eth_write(eth, EDMR_SRST, EDMR); + for (i = 0; i < TIMEOUT_CNT; i++) { + if (!(sh_eth_read(eth, EDMR) & EDMR_SRST)) break; udelay(1000); } - if (i == EDMR_INIT_CNT) { + if (i == TIMEOUT_CNT) { printf(SHETHER_NAME ": Software reset timeout\n"); ret = -EIO; } return ret; +#else + sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR); + udelay(3000); + sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR); + + return 0; +#endif } static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) { int port = eth->port, i, ret = 0; - u32 tmp_addr; + u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s); struct sh_eth_info *port_info = ð->port_info[port]; struct tx_desc_s *cur_tx_desc; /* - * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned + * Allocate rx descriptors. They must be aligned to size of struct + * tx_desc_s. */ - port_info->tx_desc_malloc = malloc(NUM_TX_DESC * - sizeof(struct tx_desc_s) + - TX_DESC_SIZE - 1); - if (!port_info->tx_desc_malloc) { - printf(SHETHER_NAME ": malloc failed\n"); + port_info->tx_desc_alloc = + memalign(sizeof(struct tx_desc_s), alloc_desc_size); + if (!port_info->tx_desc_alloc) { + printf(SHETHER_NAME ": memalign failed\n"); ret = -ENOMEM; goto err; } - tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) & - ~(TX_DESC_SIZE - 1)); + flush_cache_wback((u32)port_info->tx_desc_alloc, alloc_desc_size); + /* Make sure we use a P2 address (non-cacheable) */ - port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); + port_info->tx_desc_base = + (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc); port_info->tx_desc_cur = port_info->tx_desc_base; /* Initialize all descriptors */ @@ -330,10 +224,12 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) /* Point the controller to the tx descriptor list. Must use physical addresses */ - outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port)); - outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port)); - outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port)); - outl(0x01, TDFFR(port));/* Last discriptor bit */ + sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) + sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); + sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR); + sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */ +#endif err: return ret; @@ -342,44 +238,44 @@ err: static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) { int port = eth->port, i , ret = 0; + u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s); struct sh_eth_info *port_info = ð->port_info[port]; struct rx_desc_s *cur_rx_desc; - u32 tmp_addr; u8 *rx_buf; /* - * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned + * Allocate rx descriptors. They must be aligned to size of struct + * rx_desc_s. */ - port_info->rx_desc_malloc = malloc(NUM_RX_DESC * - sizeof(struct rx_desc_s) + - RX_DESC_SIZE - 1); - if (!port_info->rx_desc_malloc) { - printf(SHETHER_NAME ": malloc failed\n"); + port_info->rx_desc_alloc = + memalign(sizeof(struct rx_desc_s), alloc_desc_size); + if (!port_info->rx_desc_alloc) { + printf(SHETHER_NAME ": memalign failed\n"); ret = -ENOMEM; goto err; } - tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) & - ~(RX_DESC_SIZE - 1)); + flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size); + /* Make sure we use a P2 address (non-cacheable) */ - port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); + port_info->rx_desc_base = + (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc); port_info->rx_desc_cur = port_info->rx_desc_base; /* - * Allocate rx data buffers. They must be 32 bytes aligned and in - * P2 area + * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes + * aligned and in P2 area. */ - port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31); - if (!port_info->rx_buf_malloc) { - printf(SHETHER_NAME ": malloc failed\n"); + port_info->rx_buf_alloc = + memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE); + if (!port_info->rx_buf_alloc) { + printf(SHETHER_NAME ": alloc failed\n"); ret = -ENOMEM; - goto err_buf_malloc; + goto err_buf_alloc; } - tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) & - ~(32 - 1)); - port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr); + port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc); /* Initialize all descriptors */ for (cur_rx_desc = port_info->rx_desc_base, @@ -395,16 +291,18 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) cur_rx_desc->rd0 |= RD_RDLE; /* Point the controller to the rx descriptor list */ - outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port)); - outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port)); - outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port)); - outl(RDFFR_RDLF, RDFFR(port)); + sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) + sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); + sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR); + sh_eth_write(eth, RDFFR_RDLF, RDFFR); +#endif return ret; -err_buf_malloc: - free(port_info->rx_desc_malloc); - port_info->rx_desc_malloc = NULL; +err_buf_alloc: + free(port_info->rx_desc_alloc); + port_info->rx_desc_alloc = NULL; err: return ret; @@ -415,9 +313,9 @@ static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) int port = eth->port; struct sh_eth_info *port_info = ð->port_info[port]; - if (port_info->tx_desc_malloc) { - free(port_info->tx_desc_malloc); - port_info->tx_desc_malloc = NULL; + if (port_info->tx_desc_alloc) { + free(port_info->tx_desc_alloc); + port_info->tx_desc_alloc = NULL; } } @@ -426,14 +324,14 @@ static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) int port = eth->port; struct sh_eth_info *port_info = ð->port_info[port]; - if (port_info->rx_desc_malloc) { - free(port_info->rx_desc_malloc); - port_info->rx_desc_malloc = NULL; + if (port_info->rx_desc_alloc) { + free(port_info->rx_desc_alloc); + port_info->rx_desc_alloc = NULL; } - if (port_info->rx_buf_malloc) { - free(port_info->rx_buf_malloc); - port_info->rx_buf_malloc = NULL; + if (port_info->rx_buf_alloc) { + free(port_info->rx_buf_alloc); + port_info->rx_buf_alloc = NULL; } } @@ -459,114 +357,119 @@ err_tx_init: static int sh_eth_phy_config(struct sh_eth_dev *eth) { - int port = eth->port, timeout, ret = 0; + int port = eth->port, ret = 0; struct sh_eth_info *port_info = ð->port_info[port]; - u32 val; - - /* Reset phy */ - sh_eth_mii_write_phy_reg - (port, port_info->phy_addr, PHY_CTRL, PHY_C_RESET); - timeout = 10; - while (timeout--) { - val = sh_eth_mii_read_phy_reg(port, - port_info->phy_addr, PHY_CTRL); - if (!(val & PHY_C_RESET)) - break; - udelay(SH_ETH_PHY_DELAY); - } - - if (timeout < 0) { - printf(SHETHER_NAME ": phy reset timeout\n"); - ret = -EIO; - goto err_tout; - } - - /* Advertise 100/10 baseT full/half duplex */ - sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_ANA, - (PHY_A_FDX|PHY_A_HDX|PHY_A_10FDX|PHY_A_10HDX|PHY_A_EXT)); - /* Autonegotiation, normal operation, full duplex, enable tx */ - sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL, - (PHY_C_ANEGEN|PHY_C_RANEG)); - /* Wait for autonegotiation to complete */ - timeout = 100; - while (timeout--) { - val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1); - if (val & PHY_S_ANEGC) - break; - - udelay(SH_ETH_PHY_DELAY); - } - - if (timeout < 0) { - printf(SHETHER_NAME ": phy auto-negotiation failed\n"); - ret = -ETIMEDOUT; - goto err_tout; - } + struct eth_device *dev = port_info->dev; + struct phy_device *phydev; - return ret; + phydev = phy_connect( + miiphy_get_dev_by_name(dev->name), + port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE); + port_info->phydev = phydev; + phy_config(phydev); -err_tout: return ret; } static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) { int port = eth->port, ret = 0; - u32 val, phy_status; + u32 val; struct sh_eth_info *port_info = ð->port_info[port]; + struct eth_device *dev = port_info->dev; + struct phy_device *phy; /* Configure e-dmac registers */ - outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port)); - outl(0, EESIPR(port)); - outl(0, TRSCER(port)); - outl(0, TFTR(port)); - outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port)); - outl(RMCR_RST, RMCR(port)); - outl(0, RPADIR(port)); - outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port)); + sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | + (EMDR_DESC | EDMR_EL), EDMR); + + sh_eth_write(eth, 0, EESIPR); + sh_eth_write(eth, 0, TRSCER); + sh_eth_write(eth, 0, TFTR); + sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); + sh_eth_write(eth, RMCR_RST, RMCR); +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) + sh_eth_write(eth, 0, RPADIR); +#endif + sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); /* Configure e-mac registers */ - outl(0, ECSIPR(port)); + sh_eth_write(eth, 0, ECSIPR); /* Set Mac address */ - val = bd->bi_enetaddr[0] << 24 | bd->bi_enetaddr[1] << 16 | - bd->bi_enetaddr[2] << 8 | bd->bi_enetaddr[3]; - outl(val, MAHR(port)); + val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | + dev->enetaddr[2] << 8 | dev->enetaddr[3]; + sh_eth_write(eth, val, MAHR); - val = bd->bi_enetaddr[4] << 8 | bd->bi_enetaddr[5]; - outl(val, MALR(port)); + val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; + sh_eth_write(eth, val, MALR); - outl(RFLR_RFL_MIN, RFLR(port)); - outl(0, PIPR(port)); - outl(APR_AP, APR(port)); - outl(MPR_MP, MPR(port)); - outl(TPAUSER_TPAUSE, TPAUSER(port)); + sh_eth_write(eth, RFLR_RFL_MIN, RFLR); +#if defined(SH_ETH_TYPE_GETHER) + sh_eth_write(eth, 0, PIPR); +#endif +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) + sh_eth_write(eth, APR_AP, APR); + sh_eth_write(eth, MPR_MP, MPR); + sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER); +#endif +#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) + sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) + sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR); +#endif /* Configure phy */ ret = sh_eth_phy_config(eth); if (ret) { - printf(SHETHER_NAME ":i phy config timeout\n"); + printf(SHETHER_NAME ": phy config timeout\n"); goto err_phy_cfg; } - /* Read phy status to finish configuring the e-mac */ - phy_status = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1); + phy = port_info->phydev; + ret = phy_startup(phy); + if (ret) { + printf(SHETHER_NAME ": phy startup failure\n"); + return ret; + } + + val = 0; /* Set the transfer speed */ - if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) { + if (phy->speed == 100) { printf(SHETHER_NAME ": 100Base/"); - outl(GECMR_100B, GECMR(port)); - } else { +#if defined(SH_ETH_TYPE_GETHER) + sh_eth_write(eth, GECMR_100B, GECMR); +#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) + sh_eth_write(eth, 1, RTRATE); +#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \ + defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \ + defined(CONFIG_R8A7794) + val = ECMR_RTM; +#endif + } else if (phy->speed == 10) { printf(SHETHER_NAME ": 10Base/"); - outl(GECMR_10B, GECMR(port)); +#if defined(SH_ETH_TYPE_GETHER) + sh_eth_write(eth, GECMR_10B, GECMR); +#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) + sh_eth_write(eth, 0, RTRATE); +#endif + } +#if defined(SH_ETH_TYPE_GETHER) + else if (phy->speed == 1000) { + printf(SHETHER_NAME ": 1000Base/"); + sh_eth_write(eth, GECMR_1000B, GECMR); } +#endif /* Check if full duplex mode is supported by the phy */ - if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) { + if (phy->duplex) { printf("Full\n"); - outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port)); + sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), + ECMR); } else { printf("Half\n"); - outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port)); + sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR); } return ret; @@ -581,30 +484,12 @@ static void sh_eth_start(struct sh_eth_dev *eth) * Enable the e-dmac receiver only. The transmitter will be enabled when * we have something to transmit */ - outl(EDRRR_R, EDRRR(eth->port)); + sh_eth_write(eth, EDRRR_R, EDRRR); } static void sh_eth_stop(struct sh_eth_dev *eth) { - outl(~EDRRR_R, EDRRR(eth->port)); -} - -static int sh_eth_get_mac(bd_t *bd) -{ - char *s, *e; - - s = getenv("ethaddr"); - if (s != NULL) { - int i; - for (i = 0; i < 6; ++i) { - bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - } else { - puts("Please set MAC address\n"); - } - return 0; + sh_eth_write(eth, ~EDRRR_R, EDRRR); } int sh_eth_init(struct eth_device *dev, bd_t *bd) @@ -639,50 +524,62 @@ err: void sh_eth_halt(struct eth_device *dev) { struct sh_eth_dev *eth = dev->priv; - - sh_eth_reset(eth); sh_eth_stop(eth); } int sh_eth_initialize(bd_t *bd) { - int ret = 0; + int ret = 0; struct sh_eth_dev *eth = NULL; - struct eth_device *dev = NULL; + struct eth_device *dev = NULL; - eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); + eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); if (!eth) { printf(SHETHER_NAME ": %s: malloc failed\n", __func__); ret = -ENOMEM; goto err; } - dev = (struct eth_device *)malloc(sizeof(struct eth_device)); + dev = (struct eth_device *)malloc(sizeof(struct eth_device)); if (!dev) { printf(SHETHER_NAME ": %s: malloc failed\n", __func__); ret = -ENOMEM; goto err; } - memset(dev, 0, sizeof(struct eth_device)); - memset(eth, 0, sizeof(struct sh_eth_dev)); + memset(dev, 0, sizeof(struct eth_device)); + memset(eth, 0, sizeof(struct sh_eth_dev)); eth->port = CONFIG_SH_ETHER_USE_PORT; eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; - dev->priv = (void *)eth; - dev->iobase = 0; - dev->init = sh_eth_init; - dev->halt = sh_eth_halt; - dev->send = sh_eth_send; - dev->recv = sh_eth_recv; - eth->port_info[eth->port].dev = dev; - - sprintf(dev->name, SHETHER_NAME); - - /* Register Device to EtherNet subsystem */ - eth_register(dev); - - sh_eth_get_mac(bd); + dev->priv = (void *)eth; + dev->iobase = 0; + dev->init = sh_eth_init; + dev->halt = sh_eth_halt; + dev->send = sh_eth_send; + dev->recv = sh_eth_recv; + eth->port_info[eth->port].dev = dev; + + strcpy(dev->name, SHETHER_NAME); + + /* Register Device to EtherNet subsystem */ + eth_register(dev); + + bb_miiphy_buses[0].priv = eth; + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; + + if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr)) + puts("Please set MAC address\n"); return ret; @@ -696,3 +593,81 @@ err: printf(SHETHER_NAME ": Failed\n"); return ret; } + +/******* for bb_miiphy *******/ +static int sh_eth_bb_init(struct bb_miiphy_bus *bus) +{ + return 0; +} + +static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) +{ + struct sh_eth_dev *eth = bus->priv; + + sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR); + + return 0; +} + +static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct sh_eth_dev *eth = bus->priv; + + sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR); + + return 0; +} + +static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct sh_eth_dev *eth = bus->priv; + + if (v) + sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR); + else + sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR); + + return 0; +} + +static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + struct sh_eth_dev *eth = bus->priv; + + *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3; + + return 0; +} + +static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct sh_eth_dev *eth = bus->priv; + + if (v) + sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR); + else + sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR); + + return 0; +} + +static int sh_eth_bb_delay(struct bb_miiphy_bus *bus) +{ + udelay(10); + + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = "sh_eth", + .init = sh_eth_bb_init, + .mdio_active = sh_eth_bb_mdio_active, + .mdio_tristate = sh_eth_bb_mdio_tristate, + .set_mdio = sh_eth_bb_set_mdio, + .get_mdio = sh_eth_bb_get_mdio, + .set_mdc = sh_eth_bb_set_mdc, + .delay = sh_eth_bb_delay, + } +}; +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);