X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fnet%2Fsunxi_emac.c;h=7b31f8c1da998841f32e11a16d6ca632c4b4e78a;hb=c517771ae745dbba59112b8d311e41d37c0fc032;hp=5a06d68af70804b35812b396ea53d58abf54f7e0;hpb=740f41d3cbefe2068247852220226c2c3b287249;p=u-boot

diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index 5a06d68af7..7b31f8c1da 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -437,10 +437,10 @@ static int sunxi_emac_eth_recv(struct eth_device *dev)
 			printf("Received packet is too big (len=%d)\n", rx_len);
 		} else {
 			emac_inblk_32bit((void *)&regs->rx_io_data,
-					 NetRxPackets[0], rx_len);
+					 net_rx_packets[0], rx_len);
 
 			/* Pass to upper layer */
-			NetReceive(NetRxPackets[0], rx_len);
+			net_process_received_packet(net_rx_packets[0], rx_len);
 			return rx_len;
 		}
 	}
@@ -497,7 +497,7 @@ int sunxi_emac_initialize(void)
 
 	/* Configure pin mux settings for MII Ethernet */
 	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
-		sunxi_gpio_set_cfgpin(pin, SUNXI_GPA0_EMAC);
+		sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
 
 	/* Set up clock gating */
 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);