X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fnet%2Ftsec.c;h=9b5dd92fbb84a330e0ca84cff78f9dae6c135ebd;hb=e9319f111d366294b9a1e8b1f66875242a5de3dd;hp=9edba6a7b75618bac96af9919f47964b2493b063;hpb=9e5be8214ba751436e57c3be044bf6dccb9a6687;p=u-boot diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 9edba6a7b7..9b5dd92fbb 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -5,7 +5,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright 2004, 2007 Freescale Semiconductor, Inc. + * Copyright 2004-2009 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * author Andy Fleming * @@ -17,6 +17,7 @@ #include #include #include +#include #include "miiphy.h" @@ -34,8 +35,6 @@ typedef volatile struct rtxbd { #define MAXCONTROLLERS (8) -static int relocated = 0; - static struct tsec_private *privlist[MAXCONTROLLERS]; static int num_tsecs = 0; @@ -49,21 +48,21 @@ static int tsec_send(struct eth_device *dev, volatile void *packet, int length); static int tsec_recv(struct eth_device *dev); static int tsec_init(struct eth_device *dev, bd_t * bd); +static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info); static void tsec_halt(struct eth_device *dev); static void init_registers(volatile tsec_t * regs); static void startup_tsec(struct eth_device *dev); static int init_phy(struct eth_device *dev); void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); uint read_phy_reg(struct tsec_private *priv, uint regnum); -struct phy_info *get_phy_info(struct eth_device *dev); -void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); +static struct phy_info *get_phy_info(struct eth_device *dev); +static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); static void adjust_link(struct eth_device *dev); -static void relocate_cmds(void); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ && !defined(BITBANGMII) -static int tsec_miiphy_write(char *devname, unsigned char addr, +static int tsec_miiphy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value); -static int tsec_miiphy_read(char *devname, unsigned char addr, +static int tsec_miiphy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value); #endif #ifdef CONFIG_MCAST_TFTP @@ -82,7 +81,7 @@ static struct tsec_info_struct tsec_info[] = { #ifdef CONFIG_MPC85XX_FEC { .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), - .miiregs = (tsec_t *)(TSEC_BASE_ADDR), + .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), .devname = CONFIG_MPC85XX_FEC_NAME, .phyaddr = FEC_PHY_ADDR, .flags = FEC_FLAGS @@ -96,14 +95,23 @@ static struct tsec_info_struct tsec_info[] = { #endif }; +/* + * Initialize all the TSEC devices + * + * Returns the number of TSEC devices that were initialized + */ int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) { int i; + int ret, count = 0; - for (i = 0; i < num; i++) - tsec_initialize(bis, &tsecs[i]); + for (i = 0; i < num; i++) { + ret = tsec_initialize(bis, &tsecs[i]); + if (ret > 0) + count += ret; + } - return 0; + return count; } int tsec_standard_init(bd_t *bis) @@ -114,7 +122,7 @@ int tsec_standard_init(bd_t *bis) /* Initialize device structure. Returns success if PHY * initialization succeeded (i.e. if it recognizes the PHY) */ -int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) +static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) { struct eth_device *dev; int i; @@ -135,6 +143,7 @@ int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) privlist[num_tsecs++] = priv; priv->regs = tsec_info->regs; priv->phyregs = tsec_info->miiregs; + priv->phyregs_sgmii = tsec_info->miiregs_sgmii; priv->phyaddr = tsec_info->phyaddr; priv->flags = tsec_info->flags; @@ -175,7 +184,7 @@ int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) * that it returns success if the link is up, failure otherwise. * This allows u-boot to find the first active controller. */ -int tsec_init(struct eth_device *dev, bd_t * bd) +static int tsec_init(struct eth_device *dev, bd_t * bd) { uint tempval; char tmpbuf[MAC_ADDR_LEN]; @@ -197,7 +206,10 @@ int tsec_init(struct eth_device *dev, bd_t * bd) for (i = 0; i < MAC_ADDR_LEN; i++) { tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; } - regs->macstnaddr1 = *((uint *) (tmpbuf)); + tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) | + tmpbuf[3]; + + regs->macstnaddr1 = tempval; tempval = *((uint *) (tmpbuf + 4)); @@ -218,7 +230,7 @@ int tsec_init(struct eth_device *dev, bd_t * bd) } /* Writes the given phy's reg with value, using the specified MDIO regs */ -static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, +static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr, uint reg, uint value) { int timeout = 1000000; @@ -233,7 +245,8 @@ static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, /* Provide the default behavior of writing the PHY of this ethernet device */ -#define write_phy_reg(priv, regnum, value) tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value) +#define write_phy_reg(priv, regnum, value) \ + tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value) /* Reads register regnum on the device's PHY through the * specified registers. It lowers and raises the read @@ -241,7 +254,8 @@ static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, * notvalid bit cleared), and the bus to cease activity (miimind * busy bit cleared), and then returns the value */ -uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum) +static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, + uint phyid, uint regnum) { uint value; @@ -267,7 +281,8 @@ uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum) } /* #define to provide old read_phy_reg functionality without duplicating code */ -#define read_phy_reg(priv,regnum) tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum) +#define read_phy_reg(priv,regnum) \ + tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum) #define TBIANA_SETTINGS ( \ TBIANA_ASYMMETRIC_PAUSE \ @@ -275,22 +290,27 @@ uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum) | TBIANA_FULL_DUPLEX \ ) +/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ +#ifndef CONFIG_TSEC_TBICR_SETTINGS #define TBICR_SETTINGS ( \ TBICR_PHY_RESET \ - | TBICR_ANEG_ENABLE \ | TBICR_FULL_DUPLEX \ | TBICR_SPEED1_SET \ ) +#else +#define TBICR_SETTINGS CONFIG_TSEC_TBICR_SETTINGS +#endif /* CONFIG_TSEC_TBICR_SETTINGS */ + /* Configure the TBI for SGMII operation */ static void tsec_configure_serdes(struct tsec_private *priv) { - /* Access TBI PHY registers at given TSEC register offset as opposed to the - * register offset used for external PHY accesses */ - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA, + /* Access TBI PHY registers at given TSEC register offset as opposed + * to the register offset used for external PHY accesses */ + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA, TBIANA_SETTINGS); - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON, TBICON_CLK_SELECT); - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR, TBICR_SETTINGS); } @@ -302,12 +322,10 @@ static int init_phy(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; struct phy_info *curphy; - volatile tsec_t *phyregs = priv->phyregs; volatile tsec_t *regs = priv->regs; /* Assign a Physical address to the TBI */ regs->tbipa = CONFIG_SYS_TBIPA_VALUE; - phyregs->tbipa = CONFIG_SYS_TBIPA_VALUE; asm("sync"); /* Reset MII (due to new addresses) */ @@ -317,9 +335,6 @@ static int init_phy(struct eth_device *dev) asm("sync"); while (priv->phyregs->miimind & MIIMIND_BUSY) ; - if (0 == relocated) - relocate_cmds(); - /* Get the cmd structure corresponding to the attached * PHY */ curphy = get_phy_info(dev); @@ -345,7 +360,7 @@ static int init_phy(struct eth_device *dev) * Returns which value to write to the control register. * For 10/100, the value is slightly different */ -uint mii_cr_init(uint mii_reg, struct tsec_private * priv) +static uint mii_cr_init(uint mii_reg, struct tsec_private * priv) { if (priv->flags & TSEC_GIGABIT) return MIIM_CONTROL_INIT; @@ -353,18 +368,17 @@ uint mii_cr_init(uint mii_reg, struct tsec_private * priv) return MIIM_CR_INIT; } -/* Parse the status register for link, and then do - * auto-negotiation +/* + * Wait for auto-negotiation to complete, then determine link */ -uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) +static uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) { /* * Wait if the link is up, and autonegotiation is in progress * (ie - we're capable and it's not done) */ mii_reg = read_phy_reg(priv, MIIM_STATUS); - if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) - && !(mii_reg & PHY_BMSR_AUTN_COMP)) { + if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) { int i = 0; puts("Waiting for PHY auto negotiation to complete"); @@ -378,6 +392,12 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) return 0; } + if (ctrlc()) { + puts("user interrupt!\n"); + priv->link = 0; + return -EINTR; + } + if ((i++ % 1000) == 0) { putc('.'); } @@ -385,15 +405,15 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) mii_reg = read_phy_reg(priv, MIIM_STATUS); } puts(" done\n"); - priv->link = 1; + + /* Link status bit is latched low, read it again */ + mii_reg = read_phy_reg(priv, MIIM_STATUS); + udelay(500000); /* another 500 ms (results in faster booting) */ - } else { - if (mii_reg & MIIM_STATUS_LINK) - priv->link = 1; - else - priv->link = 0; } + priv->link = mii_reg & MIIM_STATUS_LINK ? 1 : 0; + return 0; } @@ -405,7 +425,7 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) * * Stolen from Linux's mii.c and phy_device.c */ -uint mii_parse_link(uint mii_reg, struct tsec_private *priv) +static uint mii_parse_link(uint mii_reg, struct tsec_private *priv) { /* We're using autonegotiation */ if (mii_reg & PHY_BMSR_AUTN_ABLE) { @@ -467,65 +487,166 @@ uint mii_parse_link(uint mii_reg, struct tsec_private *priv) return 0; } +/* + * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain + * circumstances. eg a gigabit TSEC connected to a gigabit switch with + * a 4-wire ethernet cable. Both ends advertise gigabit, but can't + * link. "Ethernet@Wirespeed" reduces advertised speed until link + * can be achieved. + */ +static uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv) +{ + return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010; +} + /* * Parse the BCM54xx status register for speed and duplex information. * The linux sungem_phy has this information, but in a table format. */ -uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) +static uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) { + /* If there is no link, speed and duplex don't matter */ + if (!priv->link) + return 0; - switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){ + switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> + MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) { + case 1: + priv->duplexity = 0; + priv->speed = 10; + break; + case 2: + priv->duplexity = 1; + priv->speed = 10; + break; + case 3: + priv->duplexity = 0; + priv->speed = 100; + break; + case 5: + priv->duplexity = 1; + priv->speed = 100; + break; + case 6: + priv->duplexity = 0; + priv->speed = 1000; + break; + case 7: + priv->duplexity = 1; + priv->speed = 1000; + break; + default: + printf("Auto-neg error, defaulting to 10BT/HD\n"); + priv->duplexity = 0; + priv->speed = 10; + break; + } - case 1: - printf("Enet starting in 10BT/HD\n"); - priv->duplexity = 0; - priv->speed = 10; - break; + return 0; +} - case 2: - printf("Enet starting in 10BT/FD\n"); - priv->duplexity = 1; - priv->speed = 10; - break; +/* + * Find out if PHY is in copper or serdes mode by looking at Expansion Reg + * 0x42 - "Operating Mode Status Register" + */ +static int BCM8482_is_serdes(struct tsec_private *priv) +{ + u16 val; + int serdes = 0; + + write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_ER | 0x42); + val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA); + + switch (val & 0x1f) { + case 0x0d: /* RGMII-to-100Base-FX */ + case 0x0e: /* RGMII-to-SGMII */ + case 0x0f: /* RGMII-to-SerDes */ + case 0x12: /* SGMII-to-SerDes */ + case 0x13: /* SGMII-to-100Base-FX */ + case 0x16: /* SerDes-to-Serdes */ + serdes = 1; + break; + case 0x6: /* RGMII-to-Copper */ + case 0x14: /* SGMII-to-Copper */ + case 0x17: /* SerDes-to-Copper */ + break; + default: + printf("ERROR, invalid PHY mode (0x%x\n)", val); + break; + } - case 3: - printf("Enet starting in 100BT/HD\n"); - priv->duplexity = 0; - priv->speed = 100; - break; + return serdes; +} - case 5: - printf("Enet starting in 100BT/FD\n"); - priv->duplexity = 1; - priv->speed = 100; - break; +/* + * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating + * Mode Status Register" + */ +uint mii_parse_BCM5482_serdes_sr(struct tsec_private *priv) +{ + u16 val; + int i = 0; - case 6: - printf("Enet starting in 1000BT/HD\n"); - priv->duplexity = 0; - priv->speed = 1000; - break; + /* Wait 1s for link - Clause 37 autonegotiation happens very fast */ + while (1) { + write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL, + MIIM_BCM54XX_EXP_SEL_ER | 0x42); + val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA); - case 7: - printf("Enet starting in 1000BT/FD\n"); - priv->duplexity = 1; - priv->speed = 1000; + if (val & 0x8000) break; - default: - printf("Auto-neg error, defaulting to 10BT/HD\n"); - priv->duplexity = 0; - priv->speed = 10; - break; + if (i++ > 1000) { + priv->link = 0; + return 1; + } + + udelay(1000); /* 1 ms */ } + priv->link = 1; + switch ((val >> 13) & 0x3) { + case (0x00): + priv->speed = 10; + break; + case (0x01): + priv->speed = 100; + break; + case (0x02): + priv->speed = 1000; + break; + } + + priv->duplexity = (val & 0x1000) == 0x1000; + return 0; +} +/* + * Figure out if BCM5482 is in serdes or copper mode and determine link + * configuration accordingly + */ +static uint mii_parse_BCM5482_sr(uint mii_reg, struct tsec_private *priv) +{ + if (BCM8482_is_serdes(priv)) { + mii_parse_BCM5482_serdes_sr(priv); + priv->flags |= TSEC_FIBER; + } else { + /* Wait for auto-negotiation to complete or fail */ + mii_parse_sr(mii_reg, priv); + + /* Parse BCM54xx copper aux status register */ + mii_reg = read_phy_reg(priv, MIIM_BCM54xx_AUXSTATUS); + mii_parse_BCM54xx_sr(mii_reg, priv); + } + + return 0; } + /* Parse the 88E1011's status register for speed and duplex * information */ -uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) +static uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) { uint speed; @@ -583,7 +704,7 @@ uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) /* Parse the RTL8211B's status register for speed and duplex * information */ -uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) +static uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) { uint speed; @@ -641,7 +762,7 @@ uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) /* Parse the cis8201's status register for speed and duplex * information */ -uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) +static uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) { uint speed; @@ -669,7 +790,7 @@ uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) /* Parse the vsc8244's status register for speed and duplex * information */ -uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) +static uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) { uint speed; @@ -697,7 +818,7 @@ uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) /* Parse the DM9161's status register for speed and duplex * information */ -uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) +static uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) { if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) priv->speed = 100; @@ -715,10 +836,10 @@ uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) /* * Hack to write all 4 PHYs with the LED values */ -uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) +static uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) { uint phyid; - volatile tsec_t *regbase = priv->phyregs; + volatile tsec_mdio_t *regbase = priv->phyregs; int timeout = 1000000; for (phyid = 0; phyid < 4; phyid++) { @@ -733,7 +854,7 @@ uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) return MIIM_CIS8204_SLEDCON_INIT; } -uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) +static uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) { if (priv->flags & TSEC_REDUCED) return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; @@ -741,7 +862,7 @@ uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) return MIIM_CIS8204_EPHYCON_INIT; } -uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) +static uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) { uint mii_data = read_phy_reg(priv, mii_reg); @@ -833,8 +954,9 @@ static void adjust_link(struct eth_device *dev) break; } - printf("Speed: %d, %s duplex\n", priv->speed, - (priv->duplexity) ? "full" : "half"); + printf("Speed: %d, %s duplex%s\n", priv->speed, + (priv->duplexity) ? "full" : "half", + (priv->flags & TSEC_FIBER) ? ", fiber mode" : ""); } else { printf("%s: No link.\n", dev->name); @@ -973,7 +1095,8 @@ static void tsec_halt(struct eth_device *dev) regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); - while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; + while ((regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)) + != (IEVENT_GRSC | IEVENT_GTSC)) ; regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); @@ -982,11 +1105,11 @@ static void tsec_halt(struct eth_device *dev) phy_run_commands(priv, priv->phyinfo->shutdown); } -struct phy_info phy_info_M88E1149S = { +static struct phy_info phy_info_M88E1149S = { 0x1410ca, "Marvell 88E1149S", 4, - (struct phy_cmd[]){ /* config */ + (struct phy_cmd[]) { /* config */ /* Reset and configure the PHY */ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, {0x1d, 0x1f, NULL}, @@ -1000,23 +1123,22 @@ struct phy_info phy_info_M88E1149S = { {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, {miim_end,} }, - (struct phy_cmd[]){ /* startup */ + (struct phy_cmd[]) { /* startup */ /* Status is read once to clear old link state */ {MIIM_STATUS, miim_read, NULL}, /* Auto-negotiate */ {MIIM_STATUS, miim_read, &mii_parse_sr}, /* Read the status */ - {MIIM_88E1011_PHY_STATUS, miim_read, - &mii_parse_88E1011_psr}, + {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, {miim_end,} }, - (struct phy_cmd[]){ /* shutdown */ + (struct phy_cmd[]) { /* shutdown */ {miim_end,} }, }; /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ -struct phy_info phy_info_BCM5461S = { +static struct phy_info phy_info_BCM5461S = { 0x02060c1, /* 5461 ID */ "Broadcom BCM5461S", 0, /* not clear to me what minor revisions we can shift away */ @@ -1043,7 +1165,7 @@ struct phy_info phy_info_BCM5461S = { }, }; -struct phy_info phy_info_BCM5464S = { +static struct phy_info phy_info_BCM5464S = { 0x02060b1, /* 5464 ID */ "Broadcom BCM5464S", 0, /* not clear to me what minor revisions we can shift away */ @@ -1070,74 +1192,105 @@ struct phy_info phy_info_BCM5464S = { }, }; -struct phy_info phy_info_M88E1011S = { +static struct phy_info phy_info_BCM5482S = { + 0x0143bcb, + "Broadcom BCM5482S", + 4, + (struct phy_cmd[]) { /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + /* Setup read from auxilary control shadow register 7 */ + {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL}, + /* Read Misc Control register and or in Ethernet@Wirespeed */ + {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + /* Initial config/enable of secondary SerDes interface */ + {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf), NULL}, + /* Write intial value to secondary SerDes Contol */ + {MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_SSD | 0, NULL}, + {MIIM_BCM54XX_EXP_DATA, MIIM_CONTROL_RESTART, NULL}, + /* Enable copper/fiber auto-detect */ + {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201)}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Determine copper/fiber, auto-negotiate, and read the result */ + {MIIM_STATUS, miim_read, &mii_parse_BCM5482_sr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + +static struct phy_info phy_info_M88E1011S = { 0x01410c6, "Marvell 88E1011S", 4, - (struct phy_cmd[]){ /* config */ - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {0x1d, 0x1f, NULL}, - {0x1e, 0x200c, NULL}, - {0x1d, 0x5, NULL}, - {0x1e, 0x0, NULL}, - {0x1e, 0x100, NULL}, - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_88E1011_PHY_STATUS, miim_read, - &mii_parse_88E1011_psr}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1d, 0x1f, NULL}, + {0x1e, 0x200c, NULL}, + {0x1d, 0x5, NULL}, + {0x1e, 0x0, NULL}, + {0x1e, 0x100, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; -struct phy_info phy_info_M88E1111S = { +static struct phy_info phy_info_M88E1111S = { 0x01410cc, "Marvell 88E1111S", 4, - (struct phy_cmd[]){ /* config */ - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {0x1b, 0x848f, &mii_m88e1111s_setmode}, - {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_88E1011_PHY_STATUS, miim_read, - &mii_parse_88E1011_psr}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1b, 0x848f, &mii_m88e1111s_setmode}, + {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; -struct phy_info phy_info_M88E1118 = { +static struct phy_info phy_info_M88E1118 = { 0x01410e1, "Marvell 88E1118", 4, - (struct phy_cmd[]){ /* config */ + (struct phy_cmd[]) { /* config */ /* Reset and configure the PHY */ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, {0x16, 0x0002, NULL}, /* Change Page Number */ @@ -1150,8 +1303,8 @@ struct phy_info phy_info_M88E1118 = { {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ + }, + (struct phy_cmd[]) { /* startup */ {0x16, 0x0000, NULL}, /* Change Page Number */ /* Status is read once to clear old link state */ {MIIM_STATUS, miim_read, NULL}, @@ -1161,17 +1314,17 @@ struct phy_info phy_info_M88E1118 = { {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ + }, + (struct phy_cmd[]) { /* shutdown */ {miim_end,} - }, + }, }; /* * Since to access LED register we need do switch the page, we * do LED configuring in the miim_read-like function as follows */ -uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv) +static uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv) { uint pg; @@ -1188,34 +1341,33 @@ uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv) return 0; } -struct phy_info phy_info_M88E1121R = { +static struct phy_info phy_info_M88E1121R = { 0x01410cb, "Marvell 88E1121R", 4, - (struct phy_cmd[]){ /* config */ - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - /* Configure leds */ - {MIIM_88E1121_PHY_LED_CTRL, miim_read, - &mii_88E1121_set_led}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - /* Disable IRQs and de-assert interrupt */ - {MIIM_88E1121_PHY_IRQ_EN, 0, NULL}, - {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - {MIIM_STATUS, miim_read, &mii_parse_sr}, - {MIIM_STATUS, miim_read, &mii_parse_link}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + /* Configure leds */ + {MIIM_88E1121_PHY_LED_CTRL, miim_read, &mii_88E1121_set_led}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + /* Disable IRQs and de-assert interrupt */ + {MIIM_88E1121_PHY_IRQ_EN, 0, NULL}, + {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + {MIIM_STATUS, miim_read, &mii_parse_sr}, + {MIIM_STATUS, miim_read, &mii_parse_link}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) @@ -1234,199 +1386,283 @@ static struct phy_info phy_info_M88E1145 = { 0x01410cd, "Marvell 88E1145", 4, - (struct phy_cmd[]){ /* config */ - /* Reset the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - - /* Errata E0, E1 */ - {29, 0x001b, NULL}, - {30, 0x418f, NULL}, - {29, 0x0016, NULL}, - {30, 0xa2da, NULL}, - - /* Configure the PHY */ - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, - NULL}, - {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - {MIIM_88E1111_PHY_LED_CONTROL, - MIIM_88E1111_PHY_LED_DIRECT, NULL}, - /* Read the Status */ - {MIIM_88E1011_PHY_STATUS, miim_read, - &mii_parse_88E1011_psr}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + /* Reset the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + + /* Errata E0, E1 */ + {29, 0x001b, NULL}, + {30, 0x418f, NULL}, + {29, 0x0016, NULL}, + {30, 0xa2da, NULL}, + + /* Configure the PHY */ + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL}, + {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL}, + /* Read the Status */ + {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; -struct phy_info phy_info_cis8204 = { +static struct phy_info phy_info_cis8204 = { 0x3f11, "Cicada Cis8204", 6, - (struct phy_cmd[]){ /* config */ - /* Override PHY config settings */ - {MIIM_CIS8201_AUX_CONSTAT, - MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, - &mii_cis8204_fixled}, - {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, - &mii_cis8204_setmode}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_CIS8201_AUX_CONSTAT, miim_read, - &mii_parse_cis8201}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, + &mii_cis8204_fixled}, + {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, + &mii_cis8204_setmode}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; /* Cicada 8201 */ -struct phy_info phy_info_cis8201 = { +static struct phy_info phy_info_cis8201 = { 0xfc41, "CIS8201", 4, - (struct phy_cmd[]){ /* config */ - /* Override PHY config settings */ - {MIIM_CIS8201_AUX_CONSTAT, - MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, - /* Set up the interface mode */ - {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, - NULL}, - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_CIS8201_AUX_CONSTAT, miim_read, - &mii_parse_cis8201}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, + /* Set up the interface mode */ + {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + +static struct phy_info phy_info_VSC8211 = { + 0xfc4b, + "Vitesse VSC8211", + 4, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, + /* Set up the interface mode */ + {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; -struct phy_info phy_info_VSC8244 = { + +static struct phy_info phy_info_VSC8244 = { 0x3f1b, "Vitesse VSC8244", 6, - (struct phy_cmd[]){ /* config */ - /* Override PHY config settings */ - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_VSC8244_AUX_CONSTAT, miim_read, - &mii_parse_vsc8244}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; -struct phy_info phy_info_VSC8601 = { - 0x00007042, - "Vitesse VSC8601", - 4, - (struct phy_cmd[]){ /* config */ - /* Override PHY config settings */ - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, +static struct phy_info phy_info_VSC8641 = { + 0x7043, + "Vitesse VSC8641", + 4, + (struct phy_cmd[]) { /* config */ + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + +static struct phy_info phy_info_VSC8221 = { + 0xfc55, + "Vitesse VSC8221", + 4, + (struct phy_cmd[]) { /* config */ + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + +static struct phy_info phy_info_VSC8601 = { + 0x00007042, + "Vitesse VSC8601", + 4, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, #ifdef CONFIG_SYS_VSC8601_SKEWFIX - {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, + {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX) - {MIIM_EXT_PAGE_ACCESS,1,NULL}, -#define VSC8101_SKEW (CONFIG_SYS_VSC8601_SKEW_TX<<14)|(CONFIG_SYS_VSC8601_SKEW_RX<<12) - {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, - {MIIM_EXT_PAGE_ACCESS,0,NULL}, + {MIIM_EXT_PAGE_ACCESS,1,NULL}, +#define VSC8101_SKEW \ + (CONFIG_SYS_VSC8601_SKEW_TX << 14) | (CONFIG_SYS_VSC8601_SKEW_RX << 12) + {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, + {MIIM_EXT_PAGE_ACCESS,0,NULL}, #endif #endif - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_VSC8244_AUX_CONSTAT, miim_read, - &mii_parse_vsc8244}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; - -struct phy_info phy_info_dm9161 = { +static struct phy_info phy_info_dm9161 = { 0x0181b88, "Davicom DM9161E", 4, - (struct phy_cmd[]){ /* config */ - {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, - /* Do not bypass the scrambler/descrambler */ - {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, - /* Clear 10BTCSR to default */ - {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, - NULL}, - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CR_INIT, NULL}, - /* Restart Auto Negotiation */ - {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_DM9161_SCSR, miim_read, - &mii_parse_dm9161_scsr}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, + /* Do not bypass the scrambler/descrambler */ + {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, + /* Clear 10BTCSR to default */ + {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CR_INIT, NULL}, + /* Restart Auto Negotiation */ + {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; + +/* micrel KSZ804 */ +static struct phy_info phy_info_ksz804 = { + 0x0022151, + "Micrel KSZ804 PHY", + 4, + (struct phy_cmd[]) { /* config */ + {PHY_BMCR, PHY_BMCR_RESET, NULL}, + {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + {PHY_BMSR, miim_read, NULL}, + {PHY_BMSR, miim_read, &mii_parse_sr}, + {PHY_BMSR, miim_read, &mii_parse_link}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + } +}; + /* a generic flavor. */ -struct phy_info phy_info_generic = { +static struct phy_info phy_info_generic = { 0, "Unknown/Generic PHY", 32, @@ -1446,8 +1682,7 @@ struct phy_info phy_info_generic = { } }; - -uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) +static uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) { unsigned int speed; if (priv->link) { @@ -1482,26 +1717,26 @@ static struct phy_info phy_info_lxt971 = { 0x0001378e, "LXT971", 4, - (struct phy_cmd[]){ /* config */ - {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ - {miim_end,} - }, - (struct phy_cmd[]){ /* startup - enable interrupts */ - /* { 0x12, 0x00f2, NULL }, */ - {MIIM_STATUS, miim_read, NULL}, - {MIIM_STATUS, miim_read, &mii_parse_sr}, - {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown - disable interrupts */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ + {miim_end,} + }, + (struct phy_cmd[]) { /* startup - enable interrupts */ + /* { 0x12, 0x00f2, NULL }, */ + {MIIM_STATUS, miim_read, NULL}, + {MIIM_STATUS, miim_read, &mii_parse_sr}, + {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown - disable interrupts */ + {miim_end,} + }, }; /* Parse the DP83865's link and auto-neg status register for speed and duplex * information */ -uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) +static uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) { switch (mii_reg & MIIM_DP83865_SPD_MASK) { @@ -1527,34 +1762,33 @@ uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) return 0; } -struct phy_info phy_info_dp83865 = { +static struct phy_info phy_info_dp83865 = { 0x20005c7, "NatSemi DP83865", 4, - (struct phy_cmd[]){ /* config */ - {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the link and auto-neg status */ - {MIIM_DP83865_LANR, miim_read, - &mii_parse_dp83865_lanr}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the link and auto-neg status */ + {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; -struct phy_info phy_info_rtl8211b = { +static struct phy_info phy_info_rtl8211b = { 0x001cc91, "RealTek RTL8211B", 4, - (struct phy_cmd[]){ /* config */ + (struct phy_cmd[]) { /* config */ /* Reset and configure the PHY */ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, @@ -1563,7 +1797,7 @@ struct phy_info phy_info_rtl8211b = { {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, {miim_end,} }, - (struct phy_cmd[]){ /* startup */ + (struct phy_cmd[]) { /* startup */ /* Status is read once to clear old link state */ {MIIM_STATUS, miim_read, NULL}, /* Auto-negotiate */ @@ -1572,16 +1806,17 @@ struct phy_info phy_info_rtl8211b = { {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr}, {miim_end,} }, - (struct phy_cmd[]){ /* shutdown */ + (struct phy_cmd[]) { /* shutdown */ {miim_end,} }, }; -struct phy_info *phy_info[] = { +static struct phy_info *phy_info[] = { &phy_info_cis8204, &phy_info_cis8201, &phy_info_BCM5461S, &phy_info_BCM5464S, + &phy_info_BCM5482S, &phy_info_M88E1011S, &phy_info_M88E1111S, &phy_info_M88E1118, @@ -1589,12 +1824,16 @@ struct phy_info *phy_info[] = { &phy_info_M88E1145, &phy_info_M88E1149S, &phy_info_dm9161, + &phy_info_ksz804, &phy_info_lxt971, + &phy_info_VSC8211, &phy_info_VSC8244, &phy_info_VSC8601, + &phy_info_VSC8641, + &phy_info_VSC8221, &phy_info_dp83865, &phy_info_rtl8211b, - &phy_info_generic, + &phy_info_generic, /* must be last; has ID 0 and 32 bit mask */ NULL }; @@ -1602,7 +1841,7 @@ struct phy_info *phy_info[] = { * all of the known PHYs to see if one matches. If so, return * it, if not, return NULL */ -struct phy_info *get_phy_info(struct eth_device *dev) +static struct phy_info *get_phy_info(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; uint phy_reg, phy_ID; @@ -1626,9 +1865,9 @@ struct phy_info *get_phy_info(struct eth_device *dev) } } - if (theInfo == NULL) { - printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID); - return NULL; + if (theInfo == &phy_info_generic) { + printf("%s: No support for PHY id %x; assuming generic\n", + dev->name, phy_ID); } else { debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); } @@ -1639,11 +1878,11 @@ struct phy_info *get_phy_info(struct eth_device *dev) /* Execute the given series of commands on the given device's * PHY, running functions as necessary */ -void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) +static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) { int i; uint result; - volatile tsec_t *phyregs = priv->phyregs; + volatile tsec_mdio_t *phyregs = priv->phyregs; phyregs->miimcfg = MIIMCFG_RESET; @@ -1671,49 +1910,6 @@ void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) } } -/* Relocate the function pointers in the phy cmd lists */ -static void relocate_cmds(void) -{ - struct phy_cmd **cmdlistptr; - struct phy_cmd *cmd; - int i, j, k; - - for (i = 0; phy_info[i]; i++) { - /* First thing's first: relocate the pointers to the - * PHY command structures (the structs were done) */ - phy_info[i] = (struct phy_info *)((uint) phy_info[i] - + gd->reloc_off); - phy_info[i]->name += gd->reloc_off; - phy_info[i]->config = - (struct phy_cmd *)((uint) phy_info[i]->config - + gd->reloc_off); - phy_info[i]->startup = - (struct phy_cmd *)((uint) phy_info[i]->startup - + gd->reloc_off); - phy_info[i]->shutdown = - (struct phy_cmd *)((uint) phy_info[i]->shutdown - + gd->reloc_off); - - cmdlistptr = &phy_info[i]->config; - j = 0; - for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) { - k = 0; - for (cmd = *cmdlistptr; - cmd->mii_reg != miim_end; - cmd++) { - /* Only relocate non-NULL pointers */ - if (cmd->funct) - cmd->funct += gd->reloc_off; - - k++; - } - j++; - } - } - - relocated = 1; -} - #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ && !defined(BITBANGMII) @@ -1723,7 +1919,7 @@ static void relocate_cmds(void) * Returns: * 0 on success */ -static int tsec_miiphy_read(char *devname, unsigned char addr, +static int tsec_miiphy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value) { unsigned short ret; @@ -1746,7 +1942,7 @@ static int tsec_miiphy_read(char *devname, unsigned char addr, * Returns: * 0 on success */ -static int tsec_miiphy_write(char *devname, unsigned char addr, +static int tsec_miiphy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) { struct tsec_private *priv = privlist[0]; @@ -1784,10 +1980,10 @@ static int tsec_miiphy_write(char *devname, unsigned char addr, static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) { - struct tsec_private *priv = privlist[1]; - volatile tsec_t *regs = priv->regs; - volatile u32 *reg_array, value; - u8 result, whichbit, whichreg; + struct tsec_private *priv = privlist[1]; + volatile tsec_t *regs = priv->regs; + volatile u32 *reg_array, value; + u8 result, whichbit, whichreg; result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); whichbit = result & 0x1f; /* the 5 LSB = which bit to set */