X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fpci%2Ffsl_pci_init.c;h=1d75a82bc3d4dc1213926b9c41ae3632e42b419e;hb=48efe65829102fe7936304c0ed96b3935800f40a;hp=ab461b45ac11810f98474e498c0bff042068fb2c;hpb=909e9bf3ae6195ac6d52f9e453fba2be8e7e947f;p=u-boot

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index ab461b45ac..1d75a82bc3 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -47,12 +47,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define FSL_PCIE_CFG_RDY	0x4b0
 #define FSL_PROG_IF_AGENT	0x1
 
-void pciauto_prescan_setup_bridge(struct pci_controller *hose,
-				pci_dev_t dev, int sub_bus);
-void pciauto_postscan_setup_bridge(struct pci_controller *hose,
-				pci_dev_t dev, int sub_bus);
-void pciauto_config_init(struct pci_controller *hose);
-
 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
 #define CONFIG_SYS_PCI_MEMORY_BUS 0
 #endif
@@ -305,10 +299,10 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 	inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
 
 	for (r = 0; r < hose->region_count; r++)
-		debug("PCI reg:%d %016llx:%016llx %016llx %08x\n", r,
+		debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
 			(u64)hose->regions[r].phys_start,
-			hose->regions[r].bus_start,
-			hose->regions[r].size,
+			(u64)hose->regions[r].bus_start,
+			(u64)hose->regions[r].size,
 			hose->regions[r].flags);
 
 	pci_register_hose(hose);
@@ -316,7 +310,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 	hose->current_busno = hose->first_busno;
 
 	out_be32(&pci->pedr, 0xffffffff);	/* Clear any errors */
-	out_be32(&pci->peer, ~0x20140);	/* Enable All Error Interupts except
+	out_be32(&pci->peer, ~0x20140);	/* Enable All Error Interrupts except
 					 * - Master abort (pci)
 					 * - Master PERR (pci)
 					 * - ICCA (PCIe)
@@ -344,7 +338,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 			setbits_be32(&pci->pdb_stat, 0x08000000);
 			(void) in_be32(&pci->pdb_stat);
 			udelay(100);
-			debug("  Asserting PCIe reset @%x = %x\n",
+			debug("  Asserting PCIe reset @%p = %x\n",
 			      &pci->pdb_stat, in_be32(&pci->pdb_stat));
 			/* clear PCIe reset */
 			clrbits_be32(&pci->pdb_stat, 0x08000000);